Patents by Inventor Mitsutoshi Higashi

Mitsutoshi Higashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8299370
    Abstract: A wiring board includes a first substrate portion including a first feed-through conductor portion in a vertical direction, a second substrate portion provided on the first substrate portion and including a second feed-through conductor portion in a vertical direction of a corresponding part to the first feed-through conductor portion, and a feed-through electrode including the first feed-through conductor portion and the second feed-through conductor portion.
    Type: Grant
    Filed: February 22, 2010
    Date of Patent: October 30, 2012
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Hideaki Sakaguchi, Akinori Shiraishi, Mitsutoshi Higashi
  • Publication number: 20120261801
    Abstract: A wiring board includes a silicon substrate with a through hole communicating with first and second substrate surfaces. A capacitor includes a capacitor part mounted on an insulating film covering the substrate first surface and including a first electrode on the insulating film, a first dielectric layer on the first electrode, and a second electrode on the first dielectric layer. A multilayer structure arranged on a wall surface defining the through hole includes the insulating film on the through hole wall surface, a first metal layer on the insulating film formed from the same material as the first electrode, a second dielectric layer on the first metal layer formed from the same material as the first dielectric layer, and a second metal layer on the second dielectric layer formed from the same material as the second electrode. The multilayer structure covers a penetration electrode in the through hole.
    Type: Application
    Filed: April 17, 2012
    Publication date: October 18, 2012
    Applicants: TAIYO YUDEN CO., LTD., SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Akihito TAKANO, Masahiro SUNOHARA, Hideaki SAKAGUCHI, Mitsutoshi HIGASHI, Kenichi OTA, Yuichi SASAJIMA
  • Publication number: 20120261832
    Abstract: A wiring board provided with a silicon substrate including a through hole that communicates a first surface and a second surface of the silicon substrate. A capacitor is formed on an insulating film, which is applied to the silicon substrate, on the first surface and a wall surface defining the through hole. A capacitor part of the capacitor includes a first electrode, a dielectric layer, and a second electrode that are sequentially deposited on the insulating film on the first surface and the wall surface of the through hole. A penetration electrode is formed in the through hole covered by the first electrode, the dielectric layer, and the second electrode of the capacitor part.
    Type: Application
    Filed: April 17, 2012
    Publication date: October 18, 2012
    Applicants: TAIYO YUDEN CO., LTD., SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Akihito TAKANO, Masahiro SUNOHARA, Hideaki SAKAGUCHI, Mitsutoshi HIGASHI, Kenichi OTA, Yuichi SASAJIMA
  • Publication number: 20120229157
    Abstract: In one embodiment, a probe card is provided. The probe card includes: a substrate having a first surface and a second surface opposite to the first surface; a through hole formed through the substrate and extending between the first surface and the second surface; an elastic member formed in the through hole to extend to the first surface; a through electrode formed in through hole to extend to the second surface; a first trace on a surface of the elastic member to be electrically connected to the through electrode; and a contact bump on the elastic member via the first trace to be electrically connected to the first trace, wherein the contact bump is electrically connected to an electrode pad formed on a DUT (device under test) when an electrical testing is performed on the DUT using the probe card.
    Type: Application
    Filed: February 23, 2012
    Publication date: September 13, 2012
    Applicant: Shinko Electric Industries Co., Ltd.
    Inventors: Akinori SHIRAISHI, Hideaki SAKAGUCHI, Mitsutoshi HIGASHI
  • Patent number: 8227909
    Abstract: There is provided a method of manufacturing a semiconductor package. The method includes: (a) providing a silicon wafer comprising a first surface and a second surface opposite to the first surface; (b) forming vias through the silicon wafer in its thickness direction; (c) forming wiring patterns on the first surface of the silicon wafer such that the wiring patterns are electrically connected to the vias; (d) bonding a MEMS element wafer comprising MEMS elements onto the second surface of the silicon wafer such that the MEMS elements are electrically connected to the vias; (e) dividing the MEMS element wafer into the respective MEMS elements; (f) bonding a lid having concave portions therein onto the second surface of the silicon wafer such that the respective MEMS elements face a corresponding one of the concave portions; and (g) dicing the lid and the silicon wafer.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: July 24, 2012
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Hideaki Sakaguchi, Mitsutoshi Higashi, Yuichi Taguchi, Akinori Shiraishi, Kei Murayama
  • Patent number: 8216884
    Abstract: A method of producing an electronic device having mounted thereon a microelectromechanical system element. The method includes forming a micromachine component and electronic component for operation of the micromachine component on a substrate to form the system element, and bonding to the substrate a lid covering an active surface of the substrate and provided with wiring patterns to define an operating space for the micromachine component and electrically connecting the electronic component and the wiring patterns of the lid at a bonded part of the substrate and the lid.
    Type: Grant
    Filed: October 24, 2008
    Date of Patent: July 10, 2012
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Mitsutoshi Higashi
  • Publication number: 20120128021
    Abstract: A light emitting device includes a light emitting element mounting component, including a cubic package component formed of a silicon member covered with a insulating layer, and the package component including a bottom portion, a sidewall portion provided to stand upright on both ends of the bottom portion respectively, and a backwall portion provided to stand upright on an innermost part of the bottom portion, and the package component in which a cavity is provided in an inner side, and a light emitting element mounted on an inner side surface of the backwall portion of the package component, and including a light emitting surface on an upper end part, wherein a plurality of said light emitting element mounting components are stacked in a depth direction of the cavity to direct toward an identical direction.
    Type: Application
    Filed: November 1, 2011
    Publication date: May 24, 2012
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Akinori SHIRAISHI, Mitsutoshi HIGASHI
  • Patent number: 8183679
    Abstract: A peeling off layer 18 is formed on an entire surface of one surface side of a support plate 10 including the inner wall surfaces respectively of a recessed part 12 for an electronic part and recessed parts 16 for posts in which the posts 20 are formed. Then, the recessed parts 16 are filled with metal to form the posts 20. Then, conductor patterns 28 are formed that electrically connect the electrode terminals 22a of the electronic part 22 inserted into the recessed part 12 to the posts 20. Then, an insulating layer covering the conductor patterns 28 is formed to form an electronic part package 30 on the one surface side of the support plate 10 through the peeling off layer 18. After that, the electronic part package 30 is separated from the support plate 10 by the peeling off layer 18.
    Type: Grant
    Filed: July 14, 2011
    Date of Patent: May 22, 2012
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Hideaki Sakaguchi, Masahiro Sunohara, Mitsutoshi Higashi
  • Patent number: 8178957
    Abstract: A method of manufacturing an electronic component device, includes the steps of preparing a wiring substrate, which includes a silicon substrate, a concave portion provided on its upper surface side, a through hole formed to penetrate the silicon substrate on a bottom surface side of the concave portion, an insulating layer formed on the silicon substrate, a penetration electrode constructed by a lower conductor portion formed to a halfway position of a height direction from a bottom portion of the through hole and a connection metal member (indium layer) formed on the lower conductor portion in the through hole, and an electronic component having a terminal metal member (gold bump) on a lower surface side, and softening the connection metal member of the wiring substrate in a heating atmosphere and then sticking the terminal metal member of the electronic component into the connection metal member and connecting thereto.
    Type: Grant
    Filed: February 11, 2010
    Date of Patent: May 15, 2012
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Yuichi Taguchi, Akinori Shiraishi, Mitsutoshi Higashi, Kei Murayama
  • Patent number: 8169073
    Abstract: External connection terminals 27 which are electrically connected to semiconductor chips 11-1, 11-2, 12-1, 12-2 and also protrude beyond the semiconductor chips 11-1, 11-2, 12-1, 12-2 are disposed on a substrate 13 of the side to which the plural semiconductor chips 11-1, 11-2, 12-1, 12-2 are connected.
    Type: Grant
    Filed: July 12, 2006
    Date of Patent: May 1, 2012
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Kei Murayama, Mitsutoshi Higashi
  • Publication number: 20120086116
    Abstract: An electronic component device includes a substrate, an electrode post made of a metal material, provide to stand on the substrate, and an electronic component whose connection electrode is connected to the electrode post, wherein the connection electrode of the electronic component and the electrode post are joined by an alloy layer including a metal which is different from the metal material of the electrode post.
    Type: Application
    Filed: August 30, 2011
    Publication date: April 12, 2012
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Yuichi TAGUCHI, Akinori Shiraishi, Mitsutoshi Higashi
  • Patent number: 8148738
    Abstract: In a semiconductor device 100, a light emitting element 120 has been mounted on an upper plane of a semiconductor substrate 102. In an impurity diffusion region of the semiconductor substrate 102, a P conducting type of a layer 104, and an N layer 106 have been formed, while an N conducting type impurity is implanted to the P layer 104, and then the implanted impurity is diffused to constitute the N layer 106. A zener diode 108 made of a semiconductor device has been formed by the P layer 104 and the N layer 106.
    Type: Grant
    Filed: June 15, 2007
    Date of Patent: April 3, 2012
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Kei Murayama, Mitsutoshi Higashi, Naoyuki Koizumi, Yuichi Taguchi, Akinori Shiraishi, Masahiro Sunohara
  • Patent number: 8137497
    Abstract: A method includes the steps of providing a first tape base material on a single side of a stiffener substrate, forming, on the stiffener substrate, a cavity for accommodating a semiconductor chip therein, inserting the stiffener substrate in the cavity and providing the stiffener substrate on the first tape base material, sealing the semiconductor chip and the stiffener substrate with a sealing resin, and removing the first tape base material and forming a build-up layer on a tape removing surface.
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: March 20, 2012
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Masahiro Sunohara, Kei Murayama, Mitsutoshi Higashi, Hideaki Sakaguchi
  • Publication number: 20120049876
    Abstract: [Problems to be solved] To provide a test-use individual substrate capable of improving testing accuracy and connecting reliability. [Means for solving the Problems] A test-use individual substrate 30 which is used for testing a semiconductor wafer, comprises a main body portion 31, thin portions 321, 322 extending from the main body portion 31 and being relatively thinner than the main body portion, and bumps 33 provided on the thin portions 321, 322. [Selected Drawing] FIG.
    Type: Application
    Filed: August 18, 2011
    Publication date: March 1, 2012
    Applicants: SHINKO ELECTRIC INDUSTRIES CO., LTD., ADVANTEST CORPORATION
    Inventors: Shigeru MATSUMURA, Kohei KATO, Katsushi SUGAI, Koichi SHIROYAMA, Mitsutoshi HIGASHI, Akinori SHIRAISHI, Hideaki SAKAGUCHI
  • Patent number: 8108993
    Abstract: A method of manufacturing a wiring substrate is disclosed. The method includes: (a) preparing a supporting substrate including a main body and a through electrode penetrating the main body, wherein the supporting substrate includes a first surface and a second surface opposite to the first surface, and a trace is formed on the second surface of the supporting substrate; (b) forming a build-up wiring structure by alternately forming a wiring layer and an insulating layer on the first surface of the supporting substrate; and (c) obtaining a wiring substrate by separating the build-up wiring structure from the supporting substrate. Step (b) includes: forming the wiring layer using the through electrode as a power feeding wiring, and step (c) includes: peeling the build-up wiring structure from the supporting substrate to obtain the wiring substrate.
    Type: Grant
    Filed: March 13, 2009
    Date of Patent: February 7, 2012
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Mitsutoshi Higashi, Kei Murayama, Masahiro Sunohara, Hideaki Sakaguchi
  • Patent number: 8106484
    Abstract: In a silicon substrate for a package, a through electrode is provided with which a through hole passing through from a bottom surface of a cavity for accommodating a chip of an electronic device to a back surface of the substrate is filled. An end part of the through electrode in the bottom surface side of the cavity has a connection part to a wiring that forms an electric circuit including the chip of the electronic device. The silicon substrate for a package is characterized in that (1) a thin film wiring is included as the wiring and the connection part is reinforced by a conductor connected to the thin film wiring and/or (2) a wire bonding part is included as the wiring and the connection part is formed by wire bonding the end part of the through electrode in the bottom surface side of the cavity.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: January 31, 2012
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Akinori Shiraishi, Kei Murayama, Yuichi Taguchi, Masahiro Sunohara, Mitsutoshi Higashi
  • Patent number: 8080122
    Abstract: There are provided a step of preparing a dummy chip, a step of forming a cavity in a stiffener substrate, a step of providing a second tape base member on one surface of the stiffener substrate, a step of inserting the dummy chip into the cavity to provide the dummy chip on the second tape base member, a step of sealing the stiffener substrate and the dummy chip with a sealing resin, a step of removing the second tape base member and forming a build-up wiring layer on a surface from which the second tape base member is removed, a step of removing the sealing resin; and a step of peeling the dummy chip from the build-up wiring layer.
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: December 20, 2011
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Masahiro Sunohara, Kei Murayama, Mitsutoshi Higashi, Hideaki Sakaguchi
  • Patent number: 8053886
    Abstract: A semiconductor package includes a wiring board and a semiconductor device mounted on the wiring board. At least one penetration hole extends from one surface of the semiconductor chip to an opposite surface of the semiconductor chip. A penetration electrode is situated inside the penetration hole without contacting a wall of the penetration hole. The penetration electrode has one end fixed to the one surface of the semiconductor chip and an opposite end protruding from the opposite surface of the semiconductor chip. A connection terminal is formed on the opposite end of the penetration electrode and electrically connected to the wiring board.
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: November 8, 2011
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Yuichi Taguchi, Mitsutoshi Higashi, Akinori Shiraishi, Hideaki Sakaguchi, Masahiro Sunohara
  • Publication number: 20110266697
    Abstract: A peeling off layer 18 is formed on an entire surface of one surface side of a support plate 10 including the inner wall surfaces respectively of a recessed part 12 for an electronic part and recessed parts 16 for posts in which the posts 20 are formed. Then, the recessed parts 16 are filled with metal to form the posts 20. Then, conductor patterns 28 are formed that electrically connect the electrode terminals 22a of the electronic part 22 inserted into the recessed part 12 to the posts 20. Then, an insulating layer covering the conductor patterns 28 is formed to form an electronic part package 30 on the one surface side of the support plate 10 through the peeling off layer 18. After that, the electronic part package 30 is separated from the support plate 10 by the peeling off layer 18.
    Type: Application
    Filed: July 14, 2011
    Publication date: November 3, 2011
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Hideaki SAKAGUCHI, Masahiro Sunohara, Mitsutoshi Higashi
  • Publication number: 20110260744
    Abstract: A probe card for conducting an electrical test on a test subject includes a substrate body including a first surface, which faces toward the test subject, and a second surface, which is opposite to the first surface. A through electrode extends through the substrate body between the first surface and the second surface. A contact bump is formed in correspondence with the electrode pad and electrically connected to the through electrode. An elastic body is filled in an accommodating portion, which is formed in the substrate body extending from the first surface toward the second surface. The contact bump is formed on the elastic body.
    Type: Application
    Filed: April 19, 2011
    Publication date: October 27, 2011
    Applicant: Shinko Electric Industries Co., LTD.
    Inventors: Akinori Shiraishi, Hideaki Sakaguchi, Mitsutoshi Higashi