Patents by Inventor Mitsutoshi Higashi
Mitsutoshi Higashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8044429Abstract: A light-emitting device including a light-emitting element and a substrate where the light-emitting element is arranged. A housing part housing the light-emitting element and having a shape that is tapered upward from the substrate and a metal frame surrounding the light-emitting element and including the side face of the housing part made into an almost mirror-polished surface are provided on the substrate.Type: GrantFiled: October 19, 2010Date of Patent: October 25, 2011Assignee: Shinko Electric Industries Co., Ltd.Inventors: Mitsutoshi Higashi, Masahiro Sunohara, Yuichi Taguchi, Akinori Shiraishi, Kei Murayama, Naoyuki Koizumi, Hideaki Sakaguchi
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Patent number: 8039967Abstract: A wiring substrate includes a silicon substrate, a through hole formed to penetrate the silicon substrate in a thickness direction, an insulating layer formed on both surfaces and side surfaces of the silicon substrate and an inner surface of the through hole, a penetration electrode formed in the through hole, a wiring layer formed on at least one surface of the silicon substrate and connected to the penetration electrode, and a metal wire terminal connected to the wiring layer and formed to extend from one surface of the silicon substrate to a side surface thereof. The metal wire terminal on the side surface of the electronic device is connected to the mounting substrate such that a substrate direction of the electronic device in which an electronic component is mounted on the wiring substrate intersects orthogonally with a substrate direction of the mounting substrate.Type: GrantFiled: January 13, 2010Date of Patent: October 18, 2011Assignee: Shinko Electric Industries Co., Ltd.Inventors: Yuichi Taguchi, Akinori Shiraishi, Mitsutoshi Higashi
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Publication number: 20110227218Abstract: In a silicon substrate for a package, a through electrode is provided with which a through hole passing through from a bottom surface of a cavity for accommodating a chip of an electronic device to a back surface of the substrate is filled. An end part of the through electrode in the bottom surface side of the cavity has a connection part to a wiring that forms an electric circuit including the chip of the electronic device. The silicon substrate for a package is characterized in that (1) a thin film wiring is included as the wiring and the connection part is reinforced by a conductor connected to the thin film wiring and/or (2) a wire bonding part is included as the wiring and the connection part is formed by wire bonding the end part of the through electrode in the bottom surface side of the cavity.Type: ApplicationFiled: May 26, 2011Publication date: September 22, 2011Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Akinori Shiraishi, Kei Murayama, Yuichi Taguchi, Masahiro Sunohara, Mitsutoshi Higashi
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Patent number: 8008120Abstract: A peeling off layer 18 is formed on an entire surface of one surface side of a support plate 10 including the inner wall surfaces respectively of a recessed part 12 for an electronic part and recessed parts 16 for posts in which the posts 20 are formed. Then, the recessed parts 16 are filled with metal to form the posts 20. Then, conductor patterns 28 are formed that electrically connect the electrode terminals 22a of the electronic part 22 inserted into the recessed part 12 to the posts 20. Then, an insulating layer covering the conductor patterns 28 is formed to form an electronic part package 30 on the one surface side of the support plate 10 through the peeling off layer 18. After that, the electronic part package 30 is separated from the support plate 10 by the peeling off layer 18.Type: GrantFiled: December 28, 2010Date of Patent: August 30, 2011Assignee: Shinko Electric Industries Co., Ltd.Inventors: Hideaki Sakaguchi, Masahiro Sunohara, Mitsutoshi Higashi
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Patent number: 7989927Abstract: In a silicon substrate for a package, a through electrode is provided with which a through hole passing through from a bottom surface of a cavity for accommodating a chip of an electronic device to a back surface of the substrate is filled. An end part of the through electrode in the bottom surface side of the cavity has a connection part to a wiring that forms an electric circuit including the chip of the electronic device. The silicon substrate for a package is characterized in that (1) a thin film wiring is included as the wiring and the connection part is reinforced by a conductor connected to the thin film wiring and/or (2) a wire bonding part is included as the wiring and the connection part is formed by wire bonding the end part of the through electrode in the bottom surface side of the cavity.Type: GrantFiled: October 24, 2008Date of Patent: August 2, 2011Assignee: Shinko Electric Industries Co., Ltd.Inventors: Akinori Shiraishi, Kei Murayama, Yuichi Taguchi, Masahiro Sunohara, Mitsutoshi Higashi
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Patent number: 7981798Abstract: The present disclosure relates to a method of manufacturing a substrate. The method includes: (a) forming through holes by applying an anisotropic etching to a silicon substrate from a first surface of the silicon substrate; (b) forming a first insulating film to cover the first surface of the silicon substrate, surfaces of the silicon substrate exposed from the through holes, and a second surface of the silicon substrate opposite to the first surface; (c) forming an opening in a portion of the first insulating film provided on the second surface, the portion of the first insulating film corresponding to an area in which the through holes are formed; (d) etching the silicon substrate using the first insulating film provided on the second surface as a mask, thereby forming a cavity in the silicon substrate; and (e) removing the first insulating film.Type: GrantFiled: September 19, 2008Date of Patent: July 19, 2011Assignee: Shinko Electric Industries Co., Ltd.Inventors: Yuichi Taguchi, Akinori Shiraishi, Masahiro Sunohara, Kei Murayama, Hideaki Sakaguchi, Mitsutoshi Higashi
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Publication number: 20110156242Abstract: There is provided a method of manufacturing a semiconductor package. The method includes: (a) providing a silicon wafer comprising a first surface and a second surface opposite to the first surface; (b) forming vias through the silicon wafer in its thickness direction; (c) forming wiring patterns on the first surface of the silicon wafer such that the wiring patterns are electrically connected to the vias; (d) bonding a MEMS element wafer comprising MEMS elements onto the second surface of the silicon wafer such that the MEMS elements are electrically connected to the vias; (e) dividing the MEMS element wafer into the respective MEMS elements; (f) bonding a lid having concave portions therein onto the second surface of the silicon wafer such that the respective MEMS elements face a corresponding one of the concave portions; and (g) dicing the lid and the silicon wafer.Type: ApplicationFiled: December 16, 2010Publication date: June 30, 2011Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Hideaki Sakaguchi, Mitsutoshi Higashi, Yuichi Taguchi, Akinori Shiraishi, Kei Murayama
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Patent number: 7964950Abstract: An electronic parts packaging structure of the present invention includes a wiring substrate having a wiring pattern, a first insulating film which is formed on the wiring substrate and which has an opening portion in a packaging area where an electronic parts is mounted, the electronic parts having a connection terminal flip-chip mounted on the wiring pattern exposed in the opening portion of the first insulating film, a second insulating film for covering the electronic parts, a via hole formed in a predetermined portion of the first and second insulating films on the wiring pattern, and an upper wiring pattern formed on the second insulating film and connected to the wiring pattern through the via hole.Type: GrantFiled: April 21, 2009Date of Patent: June 21, 2011Assignee: Shinko Electric Industries Co., Ltd.Inventors: Masahiro Sunohara, Kei Murayama, Toshinori Koyama, Kazutaka Kobayashi, Mitsutoshi Higashi
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Patent number: 7960820Abstract: A semiconductor package in which an electronic device chip is provided in a cavity of a silicon substrate stacked product constituted by stacking a plurality of silicon substrates.Type: GrantFiled: November 5, 2008Date of Patent: June 14, 2011Assignee: Shinko Electric Industries Co., Ltd.Inventors: Akinori Shiraishi, Kei Murayama, Yuichi Taguchi, Masahiro Sunohara, Mitsutoshi Higashi
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Patent number: 7952191Abstract: A semiconductor device of the present invention includes a wiring substrate, a plurality of semiconductor chips mounted on the wiring substrate, and a radiation plate arranged over a plurality of semiconductor chips, and having a cooling passage to flow water in a horizontal direction to the wiring substrate. A plurality of semiconductor chips are arranged along the cooling passage, and out of the plurality of semiconductor chips, the semiconductor chip arranged on an inflow side of the cooling passage, has a smaller amount of heat generation than the semiconductor chip arranged on an outflow side of the cooling passage. For example, a memory chip is arranged on the inflow side of the cooling passage, and a logic chip is arranged on the outflow side of the cooling passage.Type: GrantFiled: August 7, 2008Date of Patent: May 31, 2011Assignee: Shinko Electric Industries Co., Ltd.Inventors: Masahiro Sunohara, Mitsutoshi Higashi
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Patent number: 7948092Abstract: A method of manufacturing an electronic component includes the steps of: a) forming via holes penetrating through a first semiconductor substrate and a second semiconductor substrate which are bonded together by way of a connection layer; b) pattern-etching the second semiconductor substrate using the connection layer as an etch-stop layer to form trenches communicated with the via holes; and c) integrally forming first via plugs buried in the via holes and pattern wirings buried in the trenches through plating.Type: GrantFiled: November 20, 2007Date of Patent: May 24, 2011Assignee: Shinko Electric Industries Co., Ltd.Inventors: Kei Murayama, Yuichi Taguchi, Akinori Shiraishi, Masahiro Sunohara, Mitsutoshi Higashi
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Publication number: 20110092020Abstract: A peeling off layer 18 is formed on an entire surface of one surface side of a support plate 10 including the inner wall surfaces respectively of a recessed part 12 for an electronic part and recessed parts 16 for posts in which the posts 20 are formed. Then, the recessed parts 16 are filled with metal to form the posts 20. Then, conductor patterns 28 are formed that electrically connect the electrode terminals 22a of the electronic part 22 inserted into the recessed part 12 to the posts 20. Then, an insulating layer covering the conductor patterns 28 is formed to form an electronic part package 30 on the one surface side of the support plate 10 through the peeling off layer 18. After that, the electronic part package 30 is separated from the support plate 10 by the peeling off layer 18.Type: ApplicationFiled: December 28, 2010Publication date: April 21, 2011Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Hideaki SAKAGUCHI, Masahiro Sunohara, Mitsutoshi Higashi
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Patent number: 7900807Abstract: In a conductive ball mounting apparatus for mounting one conductive ball on each of a plurality of pads which are provided on a substrate and on which an adhesive is formed, the conductive ball mounting apparatus includes: a conductive ball container for containing a plurality of conductive balls therein and having an opening to pass through the plurality of conductive balls; a substrate holder disposed over the conductive ball container to face the opening, and holding the substrate in such a manner that the plurality of conductive balls and the plurality of pads face each other and the substrate is disposed over the conductive ball container with a space therebetween; and a conductive ball supplying unit for supplying the plurality of conductive balls to the plurality of pads via the opening by moving up the plurality of conductive balls.Type: GrantFiled: March 9, 2010Date of Patent: March 8, 2011Assignee: Shinko Electric Industries Co., Ltd.Inventors: Kiyoaki Iida, Kazuo Tanaka, Norio Kondo, Hideaki Sakaguchi, Mitsutoshi Higashi
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Patent number: 7897432Abstract: A peeling off layer 18 is formed on an entire surface of one surface side of a support plate 10 including the inner wall surfaces respectively of a recessed part 12 for an electronic part and recessed parts 16 for posts in which the posts 20 are formed. Then, the recessed parts 16 are filled with metal to form the posts 20. Then, conductor patterns 28 are formed that electrically connect the electrode terminals 22a of the electronic part 22 inserted into the recessed part 12 to the posts 20. Then, an insulating layer covering the conductor patterns 28 is formed to form an electronic part package 30 on the one surface side of the support plate 10 through the peeling off layer 18. After that, the electronic part package 30 is separated from the support plate 10 by the peeling off layer 18.Type: GrantFiled: September 4, 2009Date of Patent: March 1, 2011Assignee: Shinko Electric Industries Co., Ltd.Inventors: Hideaki Sakaguchi, Masahiro Sunohara, Mitsutoshi Higashi
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Patent number: 7897510Abstract: A method for manufacturing a package which includes: an etching step of etching a silicon substrate, and forming a via hole penetrating through the silicon substrate; and a step of embedding an electrically conductive material in the via hole, and forming a via plug, characterized in that the etching step includes a first etching step of forming the via hole in a straight shape, and a second etching step of forming the via hole in a taper shape.Type: GrantFiled: August 29, 2007Date of Patent: March 1, 2011Assignee: Shinko Electric Industries Co., Ltd.Inventors: Kei Murayama, Akinori Shiraishi, Masahiro Sunohara, Yuichi Taguchi, Naoyuki Koizumi, Mitsutoshi Higashi
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Patent number: 7894201Abstract: A method of manufacturing an electronic component includes the steps of a) forming a plurality of wiring boards that include first through holes penetrating through a semiconductor substrate and conductive material buried in the first through holes; b) providing conductive projections on the conductive material of any of the plurality of wiring boards; and c) bonding the plurality of wiring boards to each other and electrically connecting the conductive material of the respective wiring boards by the projections.Type: GrantFiled: November 20, 2007Date of Patent: February 22, 2011Assignee: Shinko Electric Industries Co., Ltd.Inventors: Kei Murayama, Yuichi Taguchi, Akinori Shiraishi, Masahiro Sunohara, Mitsutoshi Higashi
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Publication number: 20110032710Abstract: A light-emitting device including a light-emitting element and a substrate where the light-emitting element is arranged. A housing part housing the light-emitting element and having a shape that is tapered upward from the substrate and a metal frame surrounding the light-emitting element and including the side face of the housing part made into an almost mirror-polished surface are provided on the substrate.Type: ApplicationFiled: October 19, 2010Publication date: February 10, 2011Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Mitsutoshi Higashi, Masahiro Sunohara, Yuichi Taguchi, Akinori Shiraishi, Kei Murayama, Naoyuki Koizumi, Hideaki Sakaguchi
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Patent number: 7884632Abstract: In a semiconductor inspecting device having a contact to be electrically connected to an electrode pad formed in a semiconductor device which is an object to be measured, and a substrate provided with the contact, the contact is provided obliquely to a main surface of the substrate.Type: GrantFiled: February 12, 2009Date of Patent: February 8, 2011Assignee: Shinko Electric Electric Industries Co., Ltd.Inventors: Akinori Shiraishi, Mitsutoshi Higashi, Kei Murayama, Katsunori Yamagishi, Mitsuhiro Aizawa
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Patent number: 7882626Abstract: A method of manufacturing a wiring board having a semiconductor chip mounting surface for mounting a semiconductor chip thereon which is manufactured by a process including a step of forming a wiring layer and an insulating layer on a support board and a step of removing the support board, including a peeling layer forming step of forming a peeling layer on the support board formed by a material having a coefficient of thermal expansion which is equal to that of a semiconductor substrate constituting the semiconductor chip, and a support board removing step of removing the support board by carrying out a predetermined treatment over the peeling layer.Type: GrantFiled: February 26, 2009Date of Patent: February 8, 2011Assignee: Shinko Electric Industries Co., Ltd.Inventors: Kei Murayama, Mitsutoshi Higashi, Masahiro Sunohara
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Publication number: 20110027990Abstract: A semiconductor chip includes a semiconductor substrate, a through via provided in a through hole that passes through the semiconductor substrate, insulating layers laminated on the semiconductor substrate, a multi-layered wiring structure having a first wiring pattern and a second wiring pattern, and an external connection terminal provided on an uppermost layer of the multi-layered wiring structure, wherein the through via and the external connection terminal are connected electrically by the second wiring pattern.Type: ApplicationFiled: October 8, 2010Publication date: February 3, 2011Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Kei Murayama, Mitsutoshi Higashi