Abstract: Methods and apparatus are provided for digital linearization of an analog phase interpolator. Up to 2N desired phase values are mapped to a corresponding M bit value, where M is greater than N. A corresponding M bit value is applied to the phase interpolator to obtain a desired one of the 2N desired phase values. A linearized phase interpolator is also provided that accounts for process, voltage, temperature or aging (PVTA) variations.

Abstract: A communication system having a receiver with a linear path and a nonlinear path. As the receiver receives a data signal, it adaptively equalizes the received signal, and amplitude-limits the equalized signal in the nonlinear path using a saturable amplifier limiter or the like. A slicer extracts data from the limited equalized received signal. In the linear path, a clock recovery circuit generates a clock signal from the equalized received signal. A delay circuit in the linear path at least partially compensates for propagation delay in the limiter. Having the clock recovery occur in other than the nonlinear path, a low jitter clock is generated. The limiter enhances the vertical opening of the data eye by increasing the rise and fall times of the limited signal, providing more noise margin for the slicer to operate with and a greater timing margin in which to sample the sliced data.

Abstract: A SerDes data sampling controller that includes a gear shifting data sampling clock that zeroes the data sampling skew at the center of the unit interval during the CDR phase lock stage, and then skews the data sample timing away from the center of the unit interval as the DFE coefficients adapt during the data transfer stage. This allows the controller to implement the best (unskewed) data sample timing during the CDR phase locking stage, and then skew the data sample timing after the DFE coefficients have adapted to provide the best (skewed) data sample timing for data bit sampling during the data transfer stage. The data sampling gear shifter may apply a variable skew value to the transition sampling or quadrature (Q) data sampling clock differentially varying the quadrature (Q) transition sampling clock from the inphase (I) data sampling clock.

Abstract: An apparatus comprises a clock and data recovery system, and a loss of lock detector at least partially incorporated within or otherwise associated with the clock and data recovery system. The loss of lock detector is configured to generate a loss of lock signal responsive to phase adjustment requests generated for a clock signal in the clock and data recovery system. By way of example, the loss of lock signal may have a first logic level indicative of the phase adjustment requests occurring at a first rate associated with a lock condition and a second logic level indicative of the phase adjustment requests occurring at a second rate lower than the first rate. Absolute values of respective phase increments each associated with multiple up and down phase requests may be accumulated, and the loss of lock signal generated as a function of the accumulated phase increment absolute values.

Abstract: A signal generator circuit for reducing power consumption of out-of-band message communications between a first device including the signal generator circuit and a second device coupled to the first device comprises a switching circuit and a controller coupled to the switching circuit. The controller is operative to receive a reference clock signal and at least a first control signal indicative of a request for the first device to send a message to the second device when the first device is in a first mode of operation. The controller generates an output control signal and an output data signal. The output control signal is operative as a function of the first control signal to selectively power up the switching circuit and a transmitter driver during the first mode. The output data signal includes the message supplied to the transmitter driver for transmission to the second device during the first mode.

Abstract: Clock buffers in a clock and data recovery (CDR) system are trimmed by receiving a first transmitted clock-like data pattern in a reduced rate mode, locking the CDR using the received version of the first transmitted clock-like data pattern; and receiving a second transmitted clock-like data pattern. The first transmitted clock-like data pattern is transmitted using a first rate mode and the reduced rate mode divides the first rate mode by an integer value. The second transmitted clock-like data pattern has a run-length that is an integer division of a run-length of the first transmitted clock-like data pattern. A phase of the clock buffers is adjusted using the second transmitted clock-like data pattern. The received first transmitted clock-like data pattern has edges that correspond to only positive or negative edges of the first transmitted clock-like data pattern.

Abstract: Methods and apparatus are provided for automatic gain control in a receiver using samples taken at a desired sampling phase and target voltage level. The gain of a received signal is adjusted by obtaining a plurality of samples of the received signal substantially at a desired sampling phase (such as a center of a given unit interval), wherein at least one of the samples is taken substantially at a target voltage level; comparing the plurality of samples to determine whether the received signal has an amplitude that is substantially equal to the target voltage level; and adjusting a receiver gain based on whether the received signal amplitude is substantially equal to the target voltage level. The comparison can comprise the evaluation of a logic function, such as an exclusive OR function. The comparison can be performed over a plurality of samples to obtain an average gain update decision.

Abstract: Methods and apparatus are provided for detecting and decoding adaptive equalization training frames (having a frame marker comprised of a string of binary ones and binary zeroes). Training frames are detected by shifting the received data; inserting at least one binary value at one end of the shifted received data to generate a modified version of the received data; applying a logic function to the received data and the modified version of the received data that identifies when corresponding bit positions have different values; and detecting the frame marker when an output of the logic function has a first binary value in an approximate middle of a string of a second binary value. The training frames are decoded using a distance between the approximate center of the frame marker and a predefined binary value in an output of the logic function.

Abstract: Methods and apparatus are provided for adapting transmitter equalization coefficients based on receiver gain adaptation. Equalization coefficients of a transmitter that communicates over a channel with a receiver are adapted by determining if a gain value for an amplifier in the receiver is within a limit of the amplifier; and preventing one or more adjustments to the transmitter equalization coefficients if the gain value does not satisfy the upper or lower limit of the amplifier. The gain adjustments comprise, for example, up and down requests for the transmitter equalization coefficients. One or more enable flags can optionally be set based on whether the gain value is within the limit of the amplifier.

Abstract: In described embodiments, a Serializer-Deserializer (SerDes) receiver includes a pattern detector that allows for detection of insufficiently randomized pattern periods and low activity periods. A freeze of equalization adaptation during these periods might occur by embedding disqualifying patterns into adaptation data. Some embodiments also allow for detection of long intervals of freeze, and so delay a freeze de-assertion in order for a clock and data recovery (CDR) circuit of the receiver to regain lock to the serial data. Embedding freeze information in the receive data allows for precise synchronization of receive data and freeze.

Abstract: Disclosed is a circuit for adjusting a voltage supplied to an IC by a power supply circuit that produces a regulated-output voltage based on an output-control signal generated by a resistive voltage divider. The circuit includes a PVT detector configured to generate an interface control signal and an interface circuit (i) connected to PVT detector and to the resistive voltage divider and (ii) configured to adjust its resistance in response to the interface control signal. Adjusting the resistance of the interface circuit causes the voltage of the output-control signal to be adjusted, thus causing the power supply circuit to adjust the regulated output voltage.

Abstract: Described embodiments adjust configurable parameters of at least one filter of a communication system. The method includes conditioning, by an analog front end (AFE) of a receiver in the communication system, an input signal applied to the receiver. Sampled values of the conditioned input signal are generated and digitized. An error detection module generates an error signal based on digitized values of the input signal and a target value. A decision feedback equalizer generates an adjustment signal based on the digitized values of the input signal and values of the error signal. A summer subtracts the adjustment signal from the conditioned input signal, generating an adjusted input signal. An adaptation module determines a conditional adaptation signal based on a comparison of sampled values of the adjusted input signal and values of the error signal. The adaptation module adjusts a transfer function of at least one filter based on the conditional adaptation signal.

Abstract: Methods and apparatus are provided for equalizing a received signal. A received signal is equalized by updating one or more equalization parameters; and discarding the updated equalization parameters if one or more predefined qualifier conditions are detected during the equalizing step. The received signal can optionally be equalized using the updated equalization parameters if the predefined qualifier conditions are not detected during the equalizing step. The updated equalization parameters can optionally be stored if the one or more predefined qualifier conditions are not detected during the equalizing step.

Abstract: Methods and apparatus are provided for detecting and decoding adaptive equalization training frames (having a frame marker comprised of a string of binary ones and binary zeroes). Training frames are detected by shifting the received data; inserting at least one binary value at one end of the shifted received data to generate a modified version of the received data; applying a logic function to the received data and the modified version of the received data that identifies when corresponding bit positions have different values; and detecting the frame marker when an output of the logic function has a first binary value in an approximate middle of a string of a second binary value. The training frames are decoded using a distance between the approximate center of the frame maker and a predefined binary value in an output of the logic function.

Abstract: Methods and apparatus are provided for a clock phase generator for CDR data sampling that generates early and/or late sampling clocks, relative to ideal transition and sample points. An early sampling clock is generated by generating a plurality of transition and data sampling clock signals having a substantially uniform phase separation; and delaying at least one of the transition clock signals to generate one or more early clock signals. A late sampling clock is generated by generating a plurality of transition and data sampling clock signals having a substantially uniform phase separation; and delaying at least one of the data sampling clock signals to generate one or more late clock signals. The early clock signals can be employed, for example, in a threshold-based decision feedback equalizer. The late clock signals can be employed, for example, in a classical decision feedback equalizer.

Abstract: Methods and apparatus are provided for adapting one or more equalization parameters in a communications system by reducing group delay spread. According to one aspect of the invention, one or more equalization parameters in a communications system are adapted by detecting one or more predefined run length patterns in a received signal, such as a plurality of consecutive same-valued bits; evaluating a transition latch value for each of the detected predefined run length patterns, wherein the transition latch value provides an indication of whether the received signal is under-equalized or over-equalized; and adjusting the one or more equalization parameters of the communications system based on the evaluation of the transition latch value. The adjusted equalization parameters may be employed to equalize intersymbol interference. A data eye monitor can be employed to evaluate the transition latch value.

Abstract: A communication system that enables a specified end-user device to obtain a media file corresponding to a delayed-play entry of a content-definition table prior to the scheduled play time. To deliver the media file to the end user, a service provider requests and receives the corresponding content from a content provider, generates the media file based on the received content, and temporarily stores the media file in a storage unit associated with the service provider. The service provider then breaks the media file into a plurality of data frames and transmits them to the end-user device during an appropriate delivery-opportunity window for storage in local storage unit (e.g., a hard drive) associated with the end-user device. At the play time, the service provider transmits to the end-user device a media-activation packet to initiate rendering thereat a copy of the media file assembled from the data frames stored in the local storage unit.

Abstract: Methods and apparatus are provided for adaptive link partner transmitter equalization. According to one aspect of the invention, a local transceiver adapts one or more equalization parameters of a link partner by receiving a training frame over a channel between the link partner and the local transceiver, wherein the training frame is comprised of a predefined training pattern; adjusting one or more of the equalization parameters of the link partner; and determining whether the equalization of the channel satisfies one or more predefined criteria based on whether the predefined training pattern is properly received by the local transceiver. The predefined training pattern can be a pseudo random pattern, such as a PN11 pattern Noise margins and jitters margins for the channel can optionally be improved.

Abstract: Methods and apparatus are provided for equalizing a received signal. A received signal is equalized by determining a data rate of the received signal; obtaining one or more equalization parameters associated with the determined data rate; and equalizing the received signal using the obtained one or more equalization parameters. The equalization parameters may comprise, for example, one or more of a gain parameter, zero control for a high pass filter and one or more threshold settings for one or more latches used during the equalizing step, such as data latches or transition latches (or both).

Abstract: Methods and apparatus are provided for CDR and equalization update qualification. A block of received data comprising a plurality of multiple tone patterns is processed. Equalization adaptation and/or updates to a timing recovery process can be selectively disabled if one or more of the multiple tone patterns exceed a corresponding predefined threshold.