Patents by Inventor Mohan K. Nair
Mohan K. Nair has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10789370Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for extending a root complex to encompass an external component. A processor includes a processor core and root complex circuitry coupled to the processor core. The processor core is to execute a basic input/output system (BIOS) and an operating system (OS). The root complex circuitry includes a coherent interface port and a downstream port. The root complex circuitry is to couple to an external component via the downstream port and the coherent interface port. The BIOS, to extend a root complex beyond the root complex circuitry to encompass the external component, is to obfuscate the downstream port from the OS, define a virtual root bridge for the external component, and enable a security check at the external component to provide protection for the coherent interface port and the downstream port.Type: GrantFiled: March 27, 2017Date of Patent: September 29, 2020Assignee: INTEL CORPORATIONInventors: Mohan K. Nair, Rajesh M. Sankaran, Utkarsh Y. Kakaiya, Zhenfu Chai, David M. Lee, Pratik M. Marolia
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Publication number: 20180276394Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for extending a root complex to encompass an external component. A processor includes a processor core and root complex circuitry coupled to the processor core. The processor core is to execute a basic input/output system (BIOS) and an operating system (OS). The root complex circuitry includes a coherent interface port and a downstream port. The root complex circuitry is to couple to an external component via the downstream port and the coherent interface port. The BIOS, to extend a root complex beyond the root complex circuitry to encompass the external component, is to obfuscate the downstream port from the OS, define a virtual root bridge for the external component, and enable a security check at the external component to provide protection for the coherent interface port and the downstream port.Type: ApplicationFiled: March 27, 2017Publication date: September 27, 2018Inventors: Mohan K. Nair, Rajesh M. Sankaran, Utkarsh Y. Kakaiya, Zhenfu Chai, David M. Lee, Pratik M. Marolia
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Patent number: 9984017Abstract: This disclosure pertains to an intelligent network fabric used to connect multiple computer nodes with one or more SR-IOV devices. The intelligent fabric includes a management device and a network fabric coupled thereto. A plurality of virtual endpoint devices are coupled to the network fabric and are configured to connect with a plurality of compute nodes. In addition, the intelligent network fabric includes a root port device coupled to the network fabric which the root port is configured to connect with virtual functions within a SR-IOV device.Type: GrantFiled: December 27, 2014Date of Patent: May 29, 2018Assignee: Intel CorporationInventor: Mohan K. Nair
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Patent number: 9817787Abstract: In one embodiment, a node includes at least one core to independently execute instructions; a first host device to receive information from the at least one core and to include the information in a first packet of a first communication protocol; a selection logic coupled to the first host device to receive the first packet and to provide the first packet to a conversion logic or a first interface to communicate with a first device via a first interconnect of the first communication protocol; the conversion logic to receive the first packet under selection of the selection logic and to encapsulate the first packet into a second packet of a second communication protocol; and a second interface coupled to the conversion logic to receive the second packet and to communicate the second packet to a second device via a second interconnect of the second communication protocol. Other embodiments are described and claimed.Type: GrantFiled: March 26, 2015Date of Patent: November 14, 2017Assignee: Intel CorporationInventors: Mohan K. Nair, Brent D. Thomas, Ramamurthy Krithivas
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Patent number: 9774503Abstract: In one embodiment, a system comprises: a plurality of compute nodes having a first core, a first memory, and a first fabric; a plurality of input/output (I/O) nodes having a second core, a second memory, and a second fabric and to couple to one or more I/O devices; at least one management node to receive discovery information responsive to execution of a discovery process by the plurality of compute nodes and the plurality of I/O nodes. The discovery information may include resource request information from the plurality of compute nodes and resource availability information from the plurality of I/O nodes. The at least one management node may configure the plurality of compute nodes and the plurality of I/O nodes based thereon.Type: GrantFiled: November 3, 2014Date of Patent: September 26, 2017Assignee: Intel CorporationInventor: Mohan K. Nair
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Patent number: 9753875Abstract: In one embodiment, the present invention includes a method for receiving a request in a router from a first endpoint coupled to the router, where the request is for an aggregated completion. In turn, the router can forward the request to multiple target agents, receive a response from each of the target agents, and consolidate the responses into an aggregated completion. Then, the router can send the aggregated completion to the first endpoint. Other embodiments are described and claimed.Type: GrantFiled: January 20, 2016Date of Patent: September 5, 2017Assignee: Intel CorporationInventors: Sridhar Lakshmanamurthy, Mikal C. Hunsaker, Michael T. Klinglesmith, Blaise Fanning, Mohan K. Nair, Joseph Murray, Rohit R. Verma, Gary J. Lavelle, Robert P. Adler
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Publication number: 20160283433Abstract: In one embodiment, a node includes at least one core to independently execute instructions; a first host device to receive information from the at least one core and to include the information in a first packet of a first communication protocol; a selection logic coupled to the first host device to receive the first packet and to provide the first packet to a conversion logic or a first interface to communicate with a first device via a first interconnect of the first communication protocol; the conversion logic to receive the first packet under selection of the selection logic and to encapsulate the first packet into a second packet of a second communication protocol; and a second interface coupled to the conversion logic to receive the second packet and to communicate the second packet to a second device via a second interconnect of the second communication protocol. Other embodiments are described and claimed.Type: ApplicationFiled: March 26, 2015Publication date: September 29, 2016Inventors: Mohan K. Nair, Brent D. Thomas, Ramamurthy Krithivas
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Publication number: 20160188513Abstract: This disclosure pertains to an intelligent network fabric used to connect multiple computer nodes with one or more SR-IOV devices. The intelligent fabric includes a management device and a network fabric coupled thereto. A plurality of virtual endpoint devices are coupled to the network fabric and are configured to connect with a plurality of compute nodes. In addition, the intelligent network fabric includes a root port device coupled to the network fabric which the root port is configured to connect with virtual functions within a SR-IOV device.Type: ApplicationFiled: December 27, 2014Publication date: June 30, 2016Inventor: Mohan K. Nair
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Publication number: 20160132447Abstract: In one embodiment, the present invention includes a method for receiving a request in a router from a first endpoint coupled to the router, where the request is for an aggregated completion. In turn, the router can forward the request to multiple target agents, receive a response from each of the target agents, and consolidate the responses into an aggregated completion. Then, the router can send the aggregated completion to the first endpoint. Other embodiments are described and claimed.Type: ApplicationFiled: January 20, 2016Publication date: May 12, 2016Inventors: Sridhar Lakshmanamurthy, Mikal C. Hunsaker, Michael T. Klinglesmith, Blaise Fanning, Mohan K. Nair, Joseph Murray, Rohit R. Verma, Gary J. Lavelle, Robert P. Adler
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Publication number: 20160127191Abstract: In one embodiment, a system comprises: a plurality of compute nodes having a first core, a first memory, and a first fabric; a plurality of input/output (I/O) nodes having a second core, a second memory, and a second fabric and to couple to one or more I/O devices; at least one management node to receive discovery information responsive to execution of a discovery process by the plurality of compute nodes and the plurality of I/O nodes. The discovery information may include resource request information from the plurality of compute nodes and resource availability information from the plurality of I/O nodes. The at least one management node may configure the plurality of compute nodes and the plurality of I/O nodes based thereon.Type: ApplicationFiled: November 3, 2014Publication date: May 5, 2016Inventor: Mohan K. Nair
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Patent number: 9292465Abstract: Embodiments help dynamically configure the width of PCIe links and also determine how to best configure the appropriate link width. This helps avoid situations where PCIe links are almost always active even at very low traffic rates. Embodiments achieve these benefits based on, for example, run-time monitoring of bandwidth requirement for integrated and non-integrated ports located downstream for the PCIe controller. This provides power savings with little impact on performance. Other embodiments are discussed herein.Type: GrantFiled: December 21, 2011Date of Patent: March 22, 2016Assignee: Intel CorporationInventors: Malay Trivedi, Mohan K. Nair, Joseph Murray, Devadatta V. Bodas, James W. Alexander, Vijayendra K. Hoskoti
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Patent number: 9270576Abstract: In one embodiment, the present invention includes a method for receiving a request in a router from a first endpoint coupled to the router, where the request is for an aggregated completion. In turn, the router can forward the request to multiple target agents, receive a response from each of the target agents, and consolidate the responses into an aggregated completion. Then, the router can send the aggregated completion to the first endpoint. Other embodiments are described and claimed.Type: GrantFiled: March 13, 2014Date of Patent: February 23, 2016Assignee: Intel CorporationInventors: Sridhar Lakshmanamurthy, Mikal C. Hunsaker, Michael T. Klinglesmith, Blaise Fanning, Mohan K. Nair, Joseph Murray, Rohit R. Verma, Gary J. Lavelle, Robert P. Adler
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Patent number: 8935578Abstract: An apparatus and method are disclosed to optimize the latency and the power of a link operating inside a processor-based system. The apparatus and method include a latency meter built into a queue that does not rely on a queue-depth threshold. The apparatus and method also include feedback logic that optimizes power reduction around an increasing latency target to react to sluggish re-provisioning behavior imposed by the physical properties of the link.Type: GrantFiled: September 29, 2012Date of Patent: January 13, 2015Assignee: Intel CorporationInventors: James W. Alexander, Buck W. Gremel, Pinkesh J. Shah, Malay Trivedi, Mohan K. Nair
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Patent number: 8908688Abstract: Devices and method with hardware configured to support phantom register programming. Where phantom register programming allows a device driver for an endpoint device to program multicast registers in the device without support of the operating system.Type: GrantFiled: September 11, 2012Date of Patent: December 9, 2014Assignee: Intel CorporationInventors: Chih-Cheh Chen, Michael T. Klinglesmith, David M. Lee, John Zulauf, Itay Franko, Peter J. Elardo, Mohan K. Nair, Chris Van Beek
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Publication number: 20140258492Abstract: In one embodiment, the present invention includes a method for receiving a request in a router from a first endpoint coupled to the router, where the request is for an aggregated completion. In turn, the router can forward the request to multiple target agents, receive a response from each of the target agents, and consolidate the responses into an aggregated completion. Then, the router can send the aggregated completion to the first endpoint. Other embodiments are described and claimed.Type: ApplicationFiled: March 13, 2014Publication date: September 11, 2014Inventors: Sridhar Lakshmanamurthy, Mikal C. Hunsaker, Michael T. Klinglesmith, Blaise Fanning, Mohan K. Nair, Joseph Murray, Rohit R. Verma, Gary J. Lavelle, Robert P. Adler
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Patent number: 8711875Abstract: In one embodiment, the present invention includes a method for receiving a request in a router from a first endpoint coupled to the router, where the request is for an aggregated completion. In turn, the router can forward the request to multiple target agents, receive a response from each of the target agents, and consolidate the responses into an aggregated completion. Then, the router can send the aggregated completion to the first endpoint. Other embodiments are described and claimed.Type: GrantFiled: September 29, 2011Date of Patent: April 29, 2014Assignee: Intel CorporationInventors: Sridhar Lakshmanamurthy, Mikal C. Hunsaker, Michael T. Klinglesmith, Blaise Fanning, Mohan K. Nair, Joseph Murray, Rohit R. Verma, Gary J. Lavelle, Robert P. Adler
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Publication number: 20140095944Abstract: An apparatus and method are disclosed to optimize the latency and the power of a link operating inside a processor-based system. The apparatus and method include a latency meter built into a queue that does not rely on a queue-depth threshold. The apparatus and method also include feedback logic that optimizes power reduction around an increasing latency target to react to sluggish re-provisioning behavior imposed by the physical properties of the link.Type: ApplicationFiled: September 29, 2012Publication date: April 3, 2014Inventors: James W. Alexander, Buck W. Gremel, Pinkesh J. Shah, Malay Trivedi, Mohan K. Nair
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Publication number: 20140019654Abstract: Embodiments help dynamically configure the width of PCIe links and also determine how to best configure the appropriate link width. This helps avoid situations where PCIe links are almost always active even at very low traffic rates. Embodiments achieve these benefits based on, for example, run-time monitoring of bandwidth requirement for integrated and non-integrated ports located downstream for the PCIe controller. This provides power savings with little impact on performance. Other embodiments are discussed herein.Type: ApplicationFiled: December 21, 2011Publication date: January 16, 2014Inventors: Malay Trivedi, Mohan K. Nair, Joseph Murray, Devadatta V. Bodas, James W. Alexander, Vijayendra K. Hoskoti
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Publication number: 20130083794Abstract: In one embodiment, the present invention includes a method for receiving a request in a router from a first endpoint coupled to the router, where the request is for an aggregated completion. In turn, the router can forward the request to multiple target agents, receive a response from each of the target agents, and consolidate the responses into an aggregated completion. Then, the router can send the aggregated completion to the first endpoint. Other embodiments are described and claimed.Type: ApplicationFiled: September 29, 2011Publication date: April 4, 2013Inventors: Sridhar Lakshmanamurthy, Mikal C. Hunsaker, Michael T. Klinglesmith, Blaise Fanning, Mohan K. Nair, Joseph Murray, Rohit R. Verma, Gary J. Lavelle, Robert P. Adler
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Publication number: 20130016720Abstract: Devices and method with hardware configured to support phantom register programming. Where phantom register programming allows a device driver for an endpoint device to program multicast registers in the device without support of the operating system.Type: ApplicationFiled: September 11, 2012Publication date: January 17, 2013Inventors: Chih-Cheh Chen, Michael T. Klinglesmith, David M. Lee, John Zulauf, Itay Franko, Peter J. Elardo, Mohan K. Nair, Christopher Van Beek