Patents by Inventor Mohan K. Nair

Mohan K. Nair has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10789370
    Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for extending a root complex to encompass an external component. A processor includes a processor core and root complex circuitry coupled to the processor core. The processor core is to execute a basic input/output system (BIOS) and an operating system (OS). The root complex circuitry includes a coherent interface port and a downstream port. The root complex circuitry is to couple to an external component via the downstream port and the coherent interface port. The BIOS, to extend a root complex beyond the root complex circuitry to encompass the external component, is to obfuscate the downstream port from the OS, define a virtual root bridge for the external component, and enable a security check at the external component to provide protection for the coherent interface port and the downstream port.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: September 29, 2020
    Assignee: INTEL CORPORATION
    Inventors: Mohan K. Nair, Rajesh M. Sankaran, Utkarsh Y. Kakaiya, Zhenfu Chai, David M. Lee, Pratik M. Marolia
  • Publication number: 20180276394
    Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for extending a root complex to encompass an external component. A processor includes a processor core and root complex circuitry coupled to the processor core. The processor core is to execute a basic input/output system (BIOS) and an operating system (OS). The root complex circuitry includes a coherent interface port and a downstream port. The root complex circuitry is to couple to an external component via the downstream port and the coherent interface port. The BIOS, to extend a root complex beyond the root complex circuitry to encompass the external component, is to obfuscate the downstream port from the OS, define a virtual root bridge for the external component, and enable a security check at the external component to provide protection for the coherent interface port and the downstream port.
    Type: Application
    Filed: March 27, 2017
    Publication date: September 27, 2018
    Inventors: Mohan K. Nair, Rajesh M. Sankaran, Utkarsh Y. Kakaiya, Zhenfu Chai, David M. Lee, Pratik M. Marolia
  • Patent number: 9984017
    Abstract: This disclosure pertains to an intelligent network fabric used to connect multiple computer nodes with one or more SR-IOV devices. The intelligent fabric includes a management device and a network fabric coupled thereto. A plurality of virtual endpoint devices are coupled to the network fabric and are configured to connect with a plurality of compute nodes. In addition, the intelligent network fabric includes a root port device coupled to the network fabric which the root port is configured to connect with virtual functions within a SR-IOV device.
    Type: Grant
    Filed: December 27, 2014
    Date of Patent: May 29, 2018
    Assignee: Intel Corporation
    Inventor: Mohan K. Nair
  • Patent number: 9817787
    Abstract: In one embodiment, a node includes at least one core to independently execute instructions; a first host device to receive information from the at least one core and to include the information in a first packet of a first communication protocol; a selection logic coupled to the first host device to receive the first packet and to provide the first packet to a conversion logic or a first interface to communicate with a first device via a first interconnect of the first communication protocol; the conversion logic to receive the first packet under selection of the selection logic and to encapsulate the first packet into a second packet of a second communication protocol; and a second interface coupled to the conversion logic to receive the second packet and to communicate the second packet to a second device via a second interconnect of the second communication protocol. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: November 14, 2017
    Assignee: Intel Corporation
    Inventors: Mohan K. Nair, Brent D. Thomas, Ramamurthy Krithivas
  • Patent number: 9774503
    Abstract: In one embodiment, a system comprises: a plurality of compute nodes having a first core, a first memory, and a first fabric; a plurality of input/output (I/O) nodes having a second core, a second memory, and a second fabric and to couple to one or more I/O devices; at least one management node to receive discovery information responsive to execution of a discovery process by the plurality of compute nodes and the plurality of I/O nodes. The discovery information may include resource request information from the plurality of compute nodes and resource availability information from the plurality of I/O nodes. The at least one management node may configure the plurality of compute nodes and the plurality of I/O nodes based thereon.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: September 26, 2017
    Assignee: Intel Corporation
    Inventor: Mohan K. Nair
  • Patent number: 9753875
    Abstract: In one embodiment, the present invention includes a method for receiving a request in a router from a first endpoint coupled to the router, where the request is for an aggregated completion. In turn, the router can forward the request to multiple target agents, receive a response from each of the target agents, and consolidate the responses into an aggregated completion. Then, the router can send the aggregated completion to the first endpoint. Other embodiments are described and claimed.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: September 5, 2017
    Assignee: Intel Corporation
    Inventors: Sridhar Lakshmanamurthy, Mikal C. Hunsaker, Michael T. Klinglesmith, Blaise Fanning, Mohan K. Nair, Joseph Murray, Rohit R. Verma, Gary J. Lavelle, Robert P. Adler
  • Publication number: 20160283433
    Abstract: In one embodiment, a node includes at least one core to independently execute instructions; a first host device to receive information from the at least one core and to include the information in a first packet of a first communication protocol; a selection logic coupled to the first host device to receive the first packet and to provide the first packet to a conversion logic or a first interface to communicate with a first device via a first interconnect of the first communication protocol; the conversion logic to receive the first packet under selection of the selection logic and to encapsulate the first packet into a second packet of a second communication protocol; and a second interface coupled to the conversion logic to receive the second packet and to communicate the second packet to a second device via a second interconnect of the second communication protocol. Other embodiments are described and claimed.
    Type: Application
    Filed: March 26, 2015
    Publication date: September 29, 2016
    Inventors: Mohan K. Nair, Brent D. Thomas, Ramamurthy Krithivas
  • Publication number: 20160188513
    Abstract: This disclosure pertains to an intelligent network fabric used to connect multiple computer nodes with one or more SR-IOV devices. The intelligent fabric includes a management device and a network fabric coupled thereto. A plurality of virtual endpoint devices are coupled to the network fabric and are configured to connect with a plurality of compute nodes. In addition, the intelligent network fabric includes a root port device coupled to the network fabric which the root port is configured to connect with virtual functions within a SR-IOV device.
    Type: Application
    Filed: December 27, 2014
    Publication date: June 30, 2016
    Inventor: Mohan K. Nair
  • Publication number: 20160132447
    Abstract: In one embodiment, the present invention includes a method for receiving a request in a router from a first endpoint coupled to the router, where the request is for an aggregated completion. In turn, the router can forward the request to multiple target agents, receive a response from each of the target agents, and consolidate the responses into an aggregated completion. Then, the router can send the aggregated completion to the first endpoint. Other embodiments are described and claimed.
    Type: Application
    Filed: January 20, 2016
    Publication date: May 12, 2016
    Inventors: Sridhar Lakshmanamurthy, Mikal C. Hunsaker, Michael T. Klinglesmith, Blaise Fanning, Mohan K. Nair, Joseph Murray, Rohit R. Verma, Gary J. Lavelle, Robert P. Adler
  • Publication number: 20160127191
    Abstract: In one embodiment, a system comprises: a plurality of compute nodes having a first core, a first memory, and a first fabric; a plurality of input/output (I/O) nodes having a second core, a second memory, and a second fabric and to couple to one or more I/O devices; at least one management node to receive discovery information responsive to execution of a discovery process by the plurality of compute nodes and the plurality of I/O nodes. The discovery information may include resource request information from the plurality of compute nodes and resource availability information from the plurality of I/O nodes. The at least one management node may configure the plurality of compute nodes and the plurality of I/O nodes based thereon.
    Type: Application
    Filed: November 3, 2014
    Publication date: May 5, 2016
    Inventor: Mohan K. Nair
  • Patent number: 9292465
    Abstract: Embodiments help dynamically configure the width of PCIe links and also determine how to best configure the appropriate link width. This helps avoid situations where PCIe links are almost always active even at very low traffic rates. Embodiments achieve these benefits based on, for example, run-time monitoring of bandwidth requirement for integrated and non-integrated ports located downstream for the PCIe controller. This provides power savings with little impact on performance. Other embodiments are discussed herein.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: March 22, 2016
    Assignee: Intel Corporation
    Inventors: Malay Trivedi, Mohan K. Nair, Joseph Murray, Devadatta V. Bodas, James W. Alexander, Vijayendra K. Hoskoti
  • Patent number: 9270576
    Abstract: In one embodiment, the present invention includes a method for receiving a request in a router from a first endpoint coupled to the router, where the request is for an aggregated completion. In turn, the router can forward the request to multiple target agents, receive a response from each of the target agents, and consolidate the responses into an aggregated completion. Then, the router can send the aggregated completion to the first endpoint. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: February 23, 2016
    Assignee: Intel Corporation
    Inventors: Sridhar Lakshmanamurthy, Mikal C. Hunsaker, Michael T. Klinglesmith, Blaise Fanning, Mohan K. Nair, Joseph Murray, Rohit R. Verma, Gary J. Lavelle, Robert P. Adler
  • Patent number: 8935578
    Abstract: An apparatus and method are disclosed to optimize the latency and the power of a link operating inside a processor-based system. The apparatus and method include a latency meter built into a queue that does not rely on a queue-depth threshold. The apparatus and method also include feedback logic that optimizes power reduction around an increasing latency target to react to sluggish re-provisioning behavior imposed by the physical properties of the link.
    Type: Grant
    Filed: September 29, 2012
    Date of Patent: January 13, 2015
    Assignee: Intel Corporation
    Inventors: James W. Alexander, Buck W. Gremel, Pinkesh J. Shah, Malay Trivedi, Mohan K. Nair
  • Patent number: 8908688
    Abstract: Devices and method with hardware configured to support phantom register programming. Where phantom register programming allows a device driver for an endpoint device to program multicast registers in the device without support of the operating system.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: December 9, 2014
    Assignee: Intel Corporation
    Inventors: Chih-Cheh Chen, Michael T. Klinglesmith, David M. Lee, John Zulauf, Itay Franko, Peter J. Elardo, Mohan K. Nair, Chris Van Beek
  • Publication number: 20140258492
    Abstract: In one embodiment, the present invention includes a method for receiving a request in a router from a first endpoint coupled to the router, where the request is for an aggregated completion. In turn, the router can forward the request to multiple target agents, receive a response from each of the target agents, and consolidate the responses into an aggregated completion. Then, the router can send the aggregated completion to the first endpoint. Other embodiments are described and claimed.
    Type: Application
    Filed: March 13, 2014
    Publication date: September 11, 2014
    Inventors: Sridhar Lakshmanamurthy, Mikal C. Hunsaker, Michael T. Klinglesmith, Blaise Fanning, Mohan K. Nair, Joseph Murray, Rohit R. Verma, Gary J. Lavelle, Robert P. Adler
  • Patent number: 8711875
    Abstract: In one embodiment, the present invention includes a method for receiving a request in a router from a first endpoint coupled to the router, where the request is for an aggregated completion. In turn, the router can forward the request to multiple target agents, receive a response from each of the target agents, and consolidate the responses into an aggregated completion. Then, the router can send the aggregated completion to the first endpoint. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: April 29, 2014
    Assignee: Intel Corporation
    Inventors: Sridhar Lakshmanamurthy, Mikal C. Hunsaker, Michael T. Klinglesmith, Blaise Fanning, Mohan K. Nair, Joseph Murray, Rohit R. Verma, Gary J. Lavelle, Robert P. Adler
  • Publication number: 20140095944
    Abstract: An apparatus and method are disclosed to optimize the latency and the power of a link operating inside a processor-based system. The apparatus and method include a latency meter built into a queue that does not rely on a queue-depth threshold. The apparatus and method also include feedback logic that optimizes power reduction around an increasing latency target to react to sluggish re-provisioning behavior imposed by the physical properties of the link.
    Type: Application
    Filed: September 29, 2012
    Publication date: April 3, 2014
    Inventors: James W. Alexander, Buck W. Gremel, Pinkesh J. Shah, Malay Trivedi, Mohan K. Nair
  • Publication number: 20140019654
    Abstract: Embodiments help dynamically configure the width of PCIe links and also determine how to best configure the appropriate link width. This helps avoid situations where PCIe links are almost always active even at very low traffic rates. Embodiments achieve these benefits based on, for example, run-time monitoring of bandwidth requirement for integrated and non-integrated ports located downstream for the PCIe controller. This provides power savings with little impact on performance. Other embodiments are discussed herein.
    Type: Application
    Filed: December 21, 2011
    Publication date: January 16, 2014
    Inventors: Malay Trivedi, Mohan K. Nair, Joseph Murray, Devadatta V. Bodas, James W. Alexander, Vijayendra K. Hoskoti
  • Publication number: 20130083794
    Abstract: In one embodiment, the present invention includes a method for receiving a request in a router from a first endpoint coupled to the router, where the request is for an aggregated completion. In turn, the router can forward the request to multiple target agents, receive a response from each of the target agents, and consolidate the responses into an aggregated completion. Then, the router can send the aggregated completion to the first endpoint. Other embodiments are described and claimed.
    Type: Application
    Filed: September 29, 2011
    Publication date: April 4, 2013
    Inventors: Sridhar Lakshmanamurthy, Mikal C. Hunsaker, Michael T. Klinglesmith, Blaise Fanning, Mohan K. Nair, Joseph Murray, Rohit R. Verma, Gary J. Lavelle, Robert P. Adler
  • Publication number: 20130016720
    Abstract: Devices and method with hardware configured to support phantom register programming. Where phantom register programming allows a device driver for an endpoint device to program multicast registers in the device without support of the operating system.
    Type: Application
    Filed: September 11, 2012
    Publication date: January 17, 2013
    Inventors: Chih-Cheh Chen, Michael T. Klinglesmith, David M. Lee, John Zulauf, Itay Franko, Peter J. Elardo, Mohan K. Nair, Christopher Van Beek