Abstract: Optical cubes and optical cube assemblies for directing optical beams are provided. The optical cubes are optically transparent modules that can be adapted to reflect, transmit, and/or partially reflect and transmit optical beams. The optical cubes may include bi-direction or multi-direction beam directing elements for directing optical beams. The optical cube assemblies may include flexible chip assemblies attached to optical cubes. The chip assemblies may include vertical cavity surface-emitting lasers for emitting optical beams or receivers for receiving optical beams mounted on a flexible and electrical interconnect mounting assembly.

Abstract: An architecture that achieves high speed performance in a network protocol handler combines parallelism and pipelining in multiple programmable processors, along with specialized front-end logic at the network interface that handles time critical protocol operations. The multiple processors are interconnected via high-speed interconnect, and each processor's memory is globally accessible by other processors. Each processor has multiple threads, each capable of fully executing programs. Each processor contains embedded dynamic random access memory (DRAM). Threads within a processor are assigned the processing of various protocol functions in a parallel/pipelined fashion. Data frame processing is done by one or more of the threads to identify related frames. Related frames are dispatched to the same thread so as to minimize the overhead associated with memory accesses and general protocol processing.

Abstract: Connections between the node switch sets associated with processors in large scalable processor arrays, such as those of the butterfly variety, are arranged, like the 2-D mesh array, in rows and columns between the node switch sets. Additional sets of switches called pivot switch sets are used to accomplish this. They are added to the processors and the processor switch sets to form processor clusters. The clusters are each assigned a logical row and column location in an array. Each pivot switch set is connected to all node switch sets in the same assigned column location and to all node switch sets in the same assigned row location as the pivot set. Consequently, any two node switch sets are connected by way of a pivot set located at either (a) the intersection row of the first node set and the column of the second node set or at (b) the intersection of the column of the first node set and the row of the second node set.

Abstract: A packet switch (25.sub.1) contains input port circuits (310) and output port circuits (380) inter-connected through two parallel paths: a multi-slot central queue (350) and a low latency by-pass cross-point switching matrix (360). The central queue has one slot dedicated to each output port to store a message portion ("chunk") destined for only that output port with the remaining slots being shared for all the output ports and dynamically allocated thereamong, as the need arises. Only those chunks which are contending for the same output port are stored in the central queue; otherwise, these chunks are routed to the appropriate output ports through the cross-point switching matrix. Each receiver classifies its resident chunks (as critical or non-critical) based upon both the urgency with which that chunk must be transmitted to its destination output port and by the status of the central queue. A critical chunk, i.e.

Abstract: A synchronous communication apparatus can be tuned to ensure reliable reception of signals propagating along transmission lines. The apparatus can be used as a communication port in a high frequency, highly connected synchronous network in which all ports can be tuned by a single, remote network control device. A local data source outputs a data signal during each of a series of local clock periods. A local source delay circuit receives input data signals from the local data source, and outputs output signals delayed by all amount (mT+.DELTA.pT) relative to corresponding input data signals, where m is a positive integer or zero, and where 0<.DELTA.p<1. The amount of the delay is dependent on the value of a source delay select signal. A local data receiver receives data signals from a local receiver delay circuit. The amount of delay of the local receiver delay circuit is also selectable.

Abstract: A communication system segment having phase multiplexing. A first communication station contains a data source which sequentially outputs a series of data signals during a series of clock periods. The data source outputs one data signal from the series during each clock period. The first communication station also contains a transition buffer which has an input connected to the output of the data source. The transition buffer has a first-in, first-out mode in which the transition buffer stores a series of Q data signals output from the data source during the most recent Q clock periods, where Q is an integer greater than zero. A second communication station contains a data receiver which sequentially inputs a series of data signals during a series of clock periods. The data receiver inputs one data signal from the series during each clock period. A communication line connects the output of the data source to the input of the data receiver.

Abstract: A communication network having a service processor, a plurality of terminal nodes, and a network of switch nodes for switchably connecting the service processor to each terminal node by way of one or more connection paths. Each switch node in the communication network is connected to the service processor either directly or through one or more other switch nodes. Each terminal node of the communication network is connected to a switch node. Each switch node and each terminal node has a device identification. At least two nodes have the same device identification. Each target node having the same device identification as another node can preferably be connected to the service processor by way of at least one connection path which does not include any other node having the same device identification as the target node. All switch nodes having the same minimum connection path length may, for example, have the same device identification.

Abstract: For use by a particular node within a digital data communications network having a plurality of counter-synchronized nodes including the particular node, called the central service node (CSN), and at least one remote node, all nodes being clocked at a common frequency, each node being synchronized by its own nodal time counter and connected to at least one other node by at least one transmission segment that completes a transmission path from the CSN, method and apparatus for: (a) establishing any value of virtual transmission delay (vtd) at individual transmission segments; (b) non-destructively determining the existing vtd at individual transmission segments; and (c) establishing basal distributions of vtd throughout the network and determining the elements thereof, (a), (b), and (c) being achieved without the central service node knowing real transmission delay (rtd) and inter-nodal asynchrony anywhere within the network and without requiring the active participation of any remote node.

Abstract: A simulation engine for logically simulating a logic network, which is divided into several levels of hierarchy. At the lowest level is a logic chip which has stored in an instruction memory a sequentially executed program of logical operators and operand addresses. The operand addresses refer to an input memory of the chip. The next highest level is the logic unit, on one circuit board, comprising a plurality of such logic chips. Each of the logic chips of the unit has its input memory receiving the same data from an input bus and a local bus and provides as its output one of the bits of an output bus and one of the bits of the local bus. At the next level, called a cluster, several logic units have their input and output buses interconnected by a plurality of switch units. All the logic chips of the several logic units operate in parallel with the exchange of data through the switch units. Several clusters can be combined into a super cluster by connecting together two or more sets of switch units.