Abstract: As a layout requirement imposed on an in-phase corporate-feed circuit, there is provided only a layout requirement to equalize the electric length of a transmission line (4) between one of N T-branch units (6) which is m-th when counted from a start point of a path A, and another one of the T-branch units (6) which is (m+1)-th when counted from the start point of the path A, to that of a transmission line (8) between one of N T-branch units (10) which is m-th when counted from an end point of a path B, and another one of the T-branch units (10) which is (m+1)-th when counted from the end point of the path B. Therefore, the in-phase corporate-feed circuit can be formed in a space smaller than that in which its circuit configuration of tournament type is formed, and downsizing of the circuit size can be achieved.

Abstract: A signal generating circuit includes a control voltage setting unit (CVSU) configured to set a control voltage for a chirp signal using voltage-frequency characteristics indicating characteristics of an output frequency versus voltage; a VCO configured to alter the frequency of its output signal by the control voltage; a quadrature demodulator configured to perform quadrature demodulation of the output signal of the VCO to generate an inphase signal and a quadrature signal orthogonal to each other; and a frequency detector configured to detect the frequency of the output signal of the VCO on the basis of the inphase signal and quadrature signal. The CVSU corrects the control voltage by using the voltage-frequency characteristics derived from relationships between the control voltage and the frequency of the output signal of the VCO. The VCO generates the chirp signal based on the control voltage corrected by the CVSU.

Abstract: Synthesizers (32, 24) for synthesizing feedback signals output from a plurality of antenna modules (4) are provided. A distortion compensation signal output unit (15) derives, from a difference between a feedback signal synthesized by the synthesizers (32, 24) and a base band signal output from a modulation unit (12), a distortion compensation coefficient that provides, to the base band signal, distortion characteristics opposite to distortion characteristics of a signal radiated from the phased array antenna and outputs a predistortion signal representing the distortion compensation coefficient to a PD unit (13).

Abstract: A problem with conventional distortion pulse shift circuits is that the output timing of a pulse signal cannot be controlled unless a reset signal is used.

Abstract: A problem with conventional distortion pulse shift circuits is that the output timing of a pulse signal cannot be controlled unless a reset signal is used.

Abstract: As a layout requirement imposed on an in-phase corporate-feed circuit, there is provided only a layout requirement to equalize the electric length of a transmission line (4) between one of N T-branch units (6) which is m-th when counted from a start point of a path A, and another one of the T-branch units (6) which is (m+1)-th when counted from the start point of the path A, to that of a transmission line (8) between one of N T-branch units (10) which is m-th when counted from an end point of a path B, and another one of the T-branch units (10) which is (m+1)-th when counted from the end point of the path B. Therefore, the in-phase corporate-feed circuit can be formed in a space smaller than that in which its circuit configuration of tournament type is formed, and downsizing of the circuit size can be achieved.

Abstract: A signal generator according to the invention includes: a reference signal source configured to output a clock signal; a phase locked loop (PLL) circuit configured to generate a chirp signal as a feedback loop type circuit including a frequency divider using the clock signal; and a linearity-improvement processor configured to detect a frequency of a chirp signal of an M-th period generated by the PLL circuit where M is an integer greater than or equal to 1, and to control a division ratio of the frequency divider such that a difference between a frequency of a chirp signal generated in (M+1)-th and subsequent periods in the PLL circuit and a desired frequency becomes smaller than a difference between the detected frequency and the desired frequency.

Abstract: Filter circuitry is constituted by transversal filters which are connected in parallel to each other. The transversal filters change amplitude and a phase of an input digital signal Xin[n·Ts] and output different digital signals X1[n·Ts], X2[n·Ts], and X3[n·Ts] as respective resulting digital signals whose amplitude and phase have been changed. A phase frequency computer computes a phase ?X[n·Ts] and a frequency fX[n·Ts] of the input digital signal Xin[n·Ts] by performing phase computation and frequency computation using the digital signals X1[n·Ts], X2[n·Ts], and X3[n·Ts] output by the transversal filters.

Abstract: Synthesizers (32, 24) for synthesizing feedback signals output from a plurality of antenna modules (4) are provided. A distortion compensation signal output unit (15) derives, from a difference between a feedback signal synthesized by the synthesizers (32, 24) and a base band signal output from a modulation unit (12), a distortion compensation coefficient that provides, to the base band signal, distortion characteristics opposite to distortion characteristics of a signal radiated from the phased array antenna and outputs a predistortion signal representing the distortion compensation coefficient to a PD unit (13).

Abstract: Filter circuitry is constituted by transversal filters which are connected in parallel to each other. The transversal filters change amplitude and a phase of an input digital signal Xin[n·Ts] and output different digital signals X1[n·Ts], X2[n·Ts], and X3[n·Ts] as respective resulting digital signals whose amplitude and phase have been changed. A phase frequency computer computes a phase ?X[n·Ts] and a frequency fX[n·Ts] of the input digital signal Xin[n·Ts] by performing phase computation and frequency computation using the digital signals X1[n·Ts], X2[n·Ts], and X3[n·Ts] output by the transversal filters.

Abstract: A signal generating circuit includes a control voltage setting unit (CVSU) configured to set a control voltage for a chirp signal using voltage-frequency characteristics indicating characteristics of an output frequency versus voltage; a VCO configured to alter the frequency of its output signal by the control voltage; a quadrature demodulator configured to perform quadrature demodulation of the output signal of the VCO to generate an inphase signal and a quadrature signal orthogonal to each other; and a frequency detector configured to detect the frequency of the output signal of the VCO on the basis of the inphase signal and quadrature signal. The CVSU corrects the control voltage by using the voltage-frequency characteristics derived from relationships between the control voltage and the frequency of the output signal of the VCO. The VCO generates the chirp signal based on the control voltage corrected by the CVSU.

Abstract: A comparator 13 that detects the difference between a high frequency signal detected by a detector 12 and a feedback signal A output from a comparator 11; a comparator 14 that detects the difference between the difference detected by the comparator 13 and a feedback signal B output from an adder 18; and a loop filter 15 that passes only a prescribed low frequency band of the output signal of the comparator 14 are provided, in which an amplitude sensitivity adjuster 16 adjusts the amplitude sensitivity of a variable gain amplifier 3 in accordance with the rate of change of the signal passing through the loop filter 15, thereby controlling the gain of the variable gain amplifier 3.

Abstract: A comparator 13 that detects the difference between a high frequency signal detected by a detector 12 and a feedback signal A output from a comparator 11; a comparator 14 that detects the difference between the difference detected by the comparator 13 and a feedback signal B output from an adder 18; and a loop filter 15 that passes only a prescribed low frequency band of the output signal of the comparator 14 are provided, in which an amplitude sensitivity adjuster 16 adjusts the amplitude sensitivity of a variable gain amplifier 3 in accordance with the rate of change of the signal passing through the loop filter 15, thereby controlling the gain of the variable gain amplifier 3.

Abstract: An analog feedback amplifier is capable of suppressing extraneous phase fluctuations and broadening a bandwidth by preventing effects of a group delay element by using an amplitude regulator 21 and a delay line 24.

Abstract: An amplifier circuit is configured in such a manner that the withstand voltage between the terminals of a FET 2 (withstand voltage B) is higher than the withstand voltage between the terminals of a FET 1 (withstand voltage A), and that the gate width of the FET 1 (Wg1) is narrower than the gate width of the FET 2 (Wg2). This makes it possible to increase the gain while maintaining high output power. The narrow gate width of the FET 1 (Wg1) connected to an input terminal 3 enables reducing the size of the cascode amplifier.

Abstract: An array antenna apparatus in which an SN ratio is improved. Antenna elements having transmission modules, respectively, are arranged in plurality, wherein the plurality of transmission modules respectively have transmission signal generators that each output a transmission intermediate frequency signal, local oscillation signal generators that each output a local oscillation signal, and transmission mixers that each mix the transmission intermediate frequency signal and the local oscillation signal with each other, thereby to carry out frequency conversion to a transmission high frequency signal. A reference signal source inputs a reference signal to the transmission signal generators and the local oscillation signal generators. The transmission intermediate frequency signal and the local oscillation signal are synchronized with each other by the reference signal.

Abstract: An analog feedback amplifier is capable of suppressing extraneous phase fluctuations and broadening a bandwidth by preventing effects of a group delay element by using an amplitude regulator 21 and a delay line 24.

Abstract: A high-frequency amplifier module includes a driver-stage amplifier 3 that amplifies an RF signal input thereto from an RF input terminal 1, and a final-stage amplifier 5 that amplifies the signal amplified by the driver-stage amplifier 3 and outputs the signal after the amplification to an RF output terminal 7. The driver-stage amplifier 3 is fabricated on a silicon substrate 11, while the final-stage amplifier 5 is fabricated on a gallium arsenide substrate. This configuration downsizes the cost while maintaining a high-frequency characteristic comparable to that in the case where all components of an entire module are fabricated on a gallium arsenide substrate 71.

Abstract: A transmission module including a power supply voltage control unit that sets a power supply voltage to the high frequency amplifier in a variable manner, and a control circuit that controls an amplitude control unit, a phase control unit and the power supply voltage control unit. The control circuit and the power supply voltage control unit control the power supply voltage in accordance with an output power of the high frequency amplifier. The transmission module can carry out not only phase control but also amplitude control in a continuous manner, while suppressing amplitude and phase variation, and a high frequency amplifier in the transmission module is made highly efficient. In addition, a large directional gain, a low side lobe level and a low power consumption are achieved, as a phased array antenna apparatus using a transmission module.

Abstract: A front-end amplifier has an impedance detector that detects an impedance seen looking into an antenna side from a power amplifier from a radio-frequency signal output from the power amplifier and a radio-frequency signal reflected from the antenna, in which a control circuit decides on whether the impedance detected by the impedance detector belongs to a specific region or not, and controls, if the impedance belongs to the specific region, at least one of the bias condition of the power amplifier and the impedance of a variable-matching circuit.