Patents by Inventor Morishige Hieda
Morishige Hieda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8681913Abstract: A reception circuit is provided which can detect the beginning of data regardless of a preamble or a unique word contained or not in a received signal and regardless of coding systems for received signals. The reception circuit includes a correlation operation portion that performs a correlation operation to generate a correlation signal while sliding one symbol of reference signal in relation to a received signal. The reference signal goes to a high level during a first half symbol period and goes to a low level during a second half symbol period. The reception circuit further includes: a delay portion that outputs a delay signal by delaying the received signal for a half symbol period in relation to the received signal; and a data beginning timing detection portion that detects a beginning peak timing for the correlation signal as a beginning timing of data contained in the delay signal.Type: GrantFiled: November 12, 2011Date of Patent: March 25, 2014Assignee: Renesas Electronics CorporationInventors: Naohisa Takayama, Ryoji Hayashi, Hiroyuki Joba, Morishige Hieda
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Patent number: 8618878Abstract: A multiport amplifier and a wireless device using the same are obtained in which isolation among output terminals is improved, whereby the quality of communication is improved. The multiport amplifier includes an input hybrid, an output hybrid, a plurality of amplifiers and a plurality of gain and phase control circuits that are inserted between the input hybrid and the output hybrid, a plurality of output coupling circuits that are inserted between the output hybrid and a plurality of output terminals so that they receive output extraction signals corresponding to a plurality of output signals, and a feedback circuit including a frequency selection circuit that is inserted between the plurality of output coupling circuits and the plurality of gain and phase control circuits.Type: GrantFiled: October 1, 2009Date of Patent: December 31, 2013Assignee: Mitsubishi Electric CorporationInventors: Masatake Hangai, Kazutomi Mori, Kenichi Tajima, Yukihiro Tahara, Morishige Hieda
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Publication number: 20130214836Abstract: A phase difference detecting circuit 3 includes a sync detecting circuit 21 for detecting establishment of phase sync from phase difference signals D and U generated by a D-type flip-flop 13, and a switch 22 for supplying, unless the sync detecting circuit 21 detects the establishment of the phase sync, the control voltage Vt1 generated by the current-output-matching loop filter 15 to a voltage-controlled oscillator 4, and for supplying, when the sync detecting circuit 21 detects the establishment of the phase sync, the control voltage Vt2 generated by the voltage-output-matching loop filter 20 to the voltage-controlled oscillator 4.Type: ApplicationFiled: April 19, 2011Publication date: August 22, 2013Applicant: Mitsubishi Electric CorporationInventors: Kenichi Tajima, Hideyuki Nakamizo, Morishige Hieda
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Publication number: 20120326781Abstract: A transmission module including a power supply voltage control unit that sets a power supply voltage to the high frequency amplifier in a variable manner, and a control circuit that controls an amplitude control unit, a phase control unit and the power supply voltage control unit. The control circuit and the power supply voltage control unit control the power supply voltage in accordance with an output power of the high frequency amplifier. The transmission module can carry out not only phase control but also amplitude control in a continuous manner, while suppressing amplitude and phase variation, and a high frequency amplifier in the transmission module is made highly efficient. In addition, a large directional gain, a low side lobe level and a low power consumption are achieved, as a phased array antenna apparatus using a transmission module.Type: ApplicationFiled: March 4, 2010Publication date: December 27, 2012Applicant: Mitsubishi Electric CorporationInventors: Kazutomi Mori, Hiroyuki Joba, Yoshinori Takahashi, Tomohiro Akiyama, Ryoji Hayashi, Mitsuhiro Shimozawa, Akira Inoue, Morishige Hieda, Kiyohide Sakai, Yoshihito Hirano
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Publication number: 20120319746Abstract: An array antenna apparatus in which an SN ratio is improved. Antenna elements having transmission modules, respectively, are arranged in plurality, wherein the plurality of transmission modules respectively have transmission signal generators that each output a transmission intermediate frequency signal, local oscillation signal generators that each output a local oscillation signal, and transmission mixers that each mix the transmission intermediate frequency signal and the local oscillation signal with each other, thereby to carry out frequency conversion to a transmission high frequency signal. A reference signal source inputs a reference signal to the transmission signal generators and the local oscillation signal generators. The transmission intermediate frequency signal and the local oscillation signal are synchronized with each other by the reference signal.Type: ApplicationFiled: February 22, 2011Publication date: December 20, 2012Applicant: Mitsubishi Electric CorporationInventors: Ryoji Hayashi, Yoshihito Hirano, Kiyohide Sakai, Mitsuhiro Shimozawa, Akira Inoue, Morishige Hieda, Hiroyuki Joba, Kenichi Tajima, Yoshinori Takahashi, Kazutomi Mori, Tomohiro Akiyama
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Publication number: 20120128106Abstract: A reception circuit is provided which can detect the beginning of data regardless of a preamble or a unique word contained or not in a received signal and regardless of coding systems for received signals. The reception circuit includes a correlation operation portion that performs a correlation operation to generate a correlation signal while sliding one symbol of reference signal in relation to a received signal. The reference signal goes to a high level during a first half symbol period and goes to a low level during a second half symbol period. The reception circuit further includes: a delay portion that outputs a delay signal by delaying the reference signal for a half symbol period in relation to the received signal; and a data beginning timing detection portion that detects a beginning peak timing for the correlation signal as a beginning timing of data contained in the delay signal.Type: ApplicationFiled: November 12, 2011Publication date: May 24, 2012Inventors: Naohisa TAKAYAMA, Ryoji Hayashi, Hiroyuki Joba, Morishige Hieda
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Publication number: 20110267141Abstract: A multiport amplifier and a wireless device using the same are obtained in which isolation among output terminals is improved, whereby the quality of communication is improved. The multiport amplifier includes an input hybrid, an output hybrid, a plurality of amplifiers and a plurality of gain and phase control circuits that are inserted between the input hybrid and the output hybrid, a plurality of output coupling circuits that are inserted between the output hybrid and a plurality of output terminals so that they receive output extraction signals corresponding to a plurality of output signals, and a feedback circuit including a frequency selection circuit that is inserted between the plurality of output coupling circuits and the plurality of gain and phase control circuits.Type: ApplicationFiled: October 1, 2009Publication date: November 3, 2011Applicant: Mitsubishi Electric CorporationInventors: Masatake Hangai, Kazutomi Mori, Kenichi Tajima, Yukihiro Tahara, Morishige Hieda
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Patent number: 8018290Abstract: An output terminal 6 is provided at the connecting point 5 between the collector terminal of a transistor 1 and an open-ended stub 4 by connecting the open-ended stub 4 to the collector terminal of the transistor 1, the open-ended stub 4 having a line length equal to a quarter of the wavelength of a signal of frequency 2N·F0 or 2N times the oscillation frequency F0. In addition, an output terminal 9 is provided at a connecting point 8 located at a distance equal to a quarter of the wavelength of a signal of oscillation frequency F0 from the end of an open-ended stub 7 by connecting the open-ended stub 7 to the base terminal of the transistor 1, the open-ended stub 7 having a line length longer than a quarter of the wavelength of the signal of oscillation frequency F0.Type: GrantFiled: October 15, 2007Date of Patent: September 13, 2011Assignee: Mitsubishi Electric CorporationInventors: Hiroyuki Mizutani, Kazuhiro Nishida, Masaomi Tsuru, Kenji Kawakami, Morishige Hieda, Moriyasu Miyazaki
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Publication number: 20100045348Abstract: An output terminal 6 is provided at the connecting point 5 between the collector terminal of a transistor 1 and an open-ended stub 4 by connecting the open-ended stub 4 to the collector terminal of the transistor 1, the open-ended stub 4 having a line length equal to a quarter of the wavelength of a signal of frequency 2N·F0 or 2N times the oscillation frequency F0. In addition, an output terminal 9 is provided at a connecting point 8 located at a distance equal to a quarter of the wavelength of a signal of oscillation frequency F0 from the end of an open-ended stub 7 by connecting the open-ended stub 7 to the base terminal of the transistor 1, the open-ended stub 7 having a line length longer than a quarter of the wavelength of the signal of oscillation frequency F0.Type: ApplicationFiled: October 15, 2007Publication date: February 25, 2010Applicant: Mitsubishi Electric CorporationInventors: Hiroyuki Mizutani, Kazuhiro Nishida, Masaomi Tsuru, Kenji Kawakami, Morishige Hieda, Moriyasu Miyazaki
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Patent number: 7633357Abstract: A single pole single throw switch for controlling propagation of a high frequency signal between an input terminal (11a) and an output terminal (11b). First FET switches (14a, 14b) in which drains and sources of FETs (12a, 12b) are connected in parallel with inductors (13a, 13b) are connected in parallel. Each FET (12a, 12b) is switched between on state and off state by a voltage being applied to the gate thereof. At the frequency of the high frequency signal, each inductor (13a, 13b) connected with off capacitor of each FET (12a, 12b) resonates in parallel.Type: GrantFiled: March 24, 2004Date of Patent: December 15, 2009Assignee: Mitsubishi Electric CorporationInventors: Masatake Hangai, Morishige Hieda, Moriyasu Miyazaki
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Patent number: 7541894Abstract: A phase-shifting circuit includes: a first parallel circuit which is connected across input and output terminals of a high frequency signal, composed of a first inductor and a first switching element that exhibits a through state in an ON state and a capacitive property in an OFF state, and produces parallel resonance at a prescribed frequency when the first switching element is in the OFF state; a series circuit composed of a second inductor and a third inductor and connected in parallel with the first parallel circuit; a capacitor having its first terminal connected to a point of connection of the second and third inductors; and a second parallel circuit which is connected across a second terminal of the capacitor and a ground, composed of a fourth inductor and a second switching element that exhibits a through state in an ON state and a capacitive property in an OFF state, and produces parallel resonance at a prescribed frequency when the second switching element is in the OFF state.Type: GrantFiled: July 27, 2004Date of Patent: June 2, 2009Assignee: Mitsubishi Electric CorporationInventors: Kenichi Miyaguchi, Morishige Hieda, Tamotsu Nishino, Masatake Hangai, Moriyasu Miyazaki, Yukihisa Yoshida, Tadashi Takagi, Mikio Hatamoto
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Patent number: 7495529Abstract: Provided is a small-size phase shift circuit having a broad band characteristic. The phase shift circuit includes: a first switching element for switching between a through path and a capacitance capacity; a second switching element for switching the capacitance capacity for the through path and the ground; and a first and a second inductor having inductance. One end of the first switching element is connected to one end of the second switching element by the first inductor while the other ends of the first and the second switching element are connected to each other by the second inductor. One end of the first switching element is connected to a high-frequency signal input terminal while the other end of the first switching element is connected to a high-frequency signal output terminal. Thus, it is possible to constitute a phase device satisfying a predetermined condition.Type: GrantFiled: March 26, 2004Date of Patent: February 24, 2009Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kenichi Miyaguchi, Morishige Hieda, Tamotsu Nishino, Masatake Hangai, Moriyasu Miyazaki, Norihiro Yunoue, Hideki Hatakeyama, Yukihisa Yoshida, Tadashi Takagi
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Publication number: 20080238570Abstract: A single pole single throw switch for controlling propagation of a high frequency signal between an input terminal (11a) and an output terminal (11b). First FET switches (14a, 14b) in which drains and sources of FETs (12a, 12b) are connected in parallel with inductors (13a, 13b) are connected in parallel. Each FET (12a, 12b) is switched between on state and off state by a voltage being applied to the gate thereof. At the frequency of the high frequency signal, each inductor (13a, 13b) connected with off capacitor of each FET (12a, 12b) resonates in parallel.Type: ApplicationFiled: March 24, 2004Publication date: October 2, 2008Inventors: Masatake Hangai, Morishige Hieda, Moriyasu Miyazaki
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Publication number: 20070273456Abstract: A phase-shifting circuit includes: a first parallel circuit which is connected across input and output terminals of a high frequency signal, composed of a first inductor and a first switching element that exhibits a through state in an ON state and a capacitive property in an OFF state, and produces parallel resonance at a prescribed frequency when the first switching element is in the OFF state; a series circuit composed of a second inductor and a third inductor and connected in parallel with the first parallel circuit; a capacitor having its first terminal connected to a point of connection of the second and third inductors; and a second parallel circuit which is connected across a second terminal of the capacitor and a ground, composed of a fourth inductor and a second switching element that exhibits a through state in an ON state and a capacitive property in an OFF state, and produces parallel resonance at a prescribed frequency when the second switching element is in the OFF state.Type: ApplicationFiled: July 27, 2004Publication date: November 29, 2007Inventors: Kenichi Miyaguchi, Morishige Hieda, Tamotsu Nishino, Masatake Hangai, Moriyasu Miyazaki, Yukihisa Yoshida, Tadashi Takagi, Mikio Hatamoto
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Publication number: 20070188264Abstract: Provided is a small-size phase shift circuit having a broad band characteristic. The phase shift circuit includes: a first switching element for switching between a through path and a capacitance capacity; a second switching element for switching the capacitance capacity for the through path and the ground; and a first and a second inductor having inductance. One end of the first switching element is connected to one end of the second switching element by the first inductor while the other ends of the first and the second switching element are connected to each other by the second inductor. One end of the first switching element is connected to a high-frequency signal input terminal while the other end of the first switching element is connected to a high-frequency signal output terminal. Thus, it is possible to constitute a phase device satisfying a predetermined condition.Type: ApplicationFiled: March 26, 2004Publication date: August 16, 2007Inventors: Kenichi Miyaguchi, Morishige Hieda, Tamotsu Nishino, Masatake Hangai, Moriyasu Miyazaki, Norihiro Yunoue, Hideki Hatakeyama, Yukihisa Yoshida, Tadashi Takagi
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Patent number: 7167064Abstract: A phase shift circuit and a phase shifter are achieved which are small in size and wide in bandwidth. The phase shift circuit includes a capacitor, and a series circuit composed of a switching element which exhibits capacitivity when it is in an off-state and an inductor connected in series with this switching element, the series circuit being connected in parallel with the capacitor. The capacitor and one terminal of the series circuit are connected with a high frequency signal input/output terminal, and the other terminal thereof is connected with ground.Type: GrantFiled: January 7, 2003Date of Patent: January 23, 2007Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kenichi Miyaguchi, Morishige Hieda, Michiaki Kasahara, Tadashi Takagi, Mikio Hatamoto
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Patent number: 7123116Abstract: A phase shifter includes an FET 2a having its drain electrode connected to an input/output terminal 1a; and FET 2b having its drain electrode connected to the source electrode of the FET 2a and its source electrode connected to an input/output terminal 1b; and FET 2c having its drain electrode connected to the source electrode of the FET 2a; and an inductor 3a having its first terminal connected to the source electrode of the FET 2c and its second terminal connected to a ground. It can reduce the insertion loss by narrowing the gate width of the FET 2a, and carries out the phase shift of a high-frequency signal with suppressing the reflection.Type: GrantFiled: March 26, 2002Date of Patent: October 17, 2006Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Morishige Hieda, Kenichi Miyaguchi, Michiaki Kasahara, Tadashi Takagi, Hiroshi Ikematsu, Norio Takeuchi, Hiromasa Nakaguro, Kazuyoshi Inami
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Publication number: 20040145429Abstract: A phase shifter includes an FET 2a having its drain electrode connected to an input/output terminal 1a; an FET 2b having its drain electrode connected to the source electrode of the FET 2a and its source electrode connected to an input/output terminal 1b; an FET 2c having its drain electrode connected to the source electrode of the FET 2a; and an inductor 3a having its first terminal connected to the source electrode of the FET 2c and its second terminal connected to a ground. It can reduce the insertion loss by narrowing the gate width of the FET 2a, and carries out the phase shift of a high-frequency signal with suppressing the reflection.Type: ApplicationFiled: October 30, 2003Publication date: July 29, 2004Inventors: Morishige Hieda, Kenichi Miyaguchi, Michiaki Kasahara, Tadashi Takagi, Hiroshi Ikematsu, Norio Takeuchi, Hiromasa Nakaguro, Kazuyoshi Inami
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Publication number: 20040085112Abstract: A phase shift circuit and a phase shifter are achieved which are small in size and wide in bandwidth. The phase shift circuit includes a capacitor, and a series circuit composed of a switching element which exhibits capacitivity when it is in an off-state and an inductor connected in series with this switching element, the series circuit being connected in parallel with the capacitor. The capacitor and one terminal of the series circuit are connected with a high frequency signal input/output terminal, and the other terminal thereof is connected with ground.Type: ApplicationFiled: September 9, 2003Publication date: May 6, 2004Inventors: Kenichi Miyaguchi, Morishige Hieda, Michiaki Kasahara, Tadashi Takagi, Mikio Hatamoto
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Patent number: 6674341Abstract: A miniaturized phase shifter and a multi-bit phase shifter are provided, in which filters are constructed using capacitors at FET pinch-off and pass phase can be shifted by turning the FET on and off, the phase shifter including: a first FET having a drain electrode connected to an input terminal and a source electrode connected to an output terminal; a second FET, in which one of a drain electrode and a source electrode thereof is connected to the source electrode of the first FET and the other is connected to ground via a first inductor; and a third FET, in which one of a drain electrode and a source electrode thereof is connected to the drain electrode of the first FET and the other is connected to ground via a second inductor.Type: GrantFiled: August 27, 2002Date of Patent: January 6, 2004Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Morishige Hieda, Kenichi Miyaguchi, Kazutomi Mori, Michiaki Kasahara, Tadashi Takagi, Hiroshi Ikematsu, Norio Takeuchi, Hiromasa Nakaguro, Kazuyoshi Inami