Abstract: The scan line drive circuit outputs selection signals GV3 and GV4 to select scan lines in the display panel. Assuming that a period in which a data voltage SV1 after being subjected to inversion of the polarity thereof is supplied to a data line in the display panel is a first period TSD, and that a period in which the data voltage SV1 after not being subjected to inversion of the polarity thereof is supplied to the data line is a second period TSC, the period TPD from the start of the first period TSD until the selection signal GV4 is activated is longer than the period TPC from the start of the second period TSC until the selection signal GV3 is activated.

Abstract: A driver includes a power supply circuit having first to n-th boost circuits, a circuit that operates based on power supplied from the power supply circuit, and an abnormality detection circuit. The abnormality detection circuit detects an abnormality of an i-th boosted voltage that is generated based on a boost operation of an i-th boost circuit. If an abnormality of the i-th boosted voltage is detected, a j-th boost circuit performs a low-capacity boost operation with a lower current-supply capacity than an ordinary boost operation or stops the boost operation.

Abstract: A display panel has a first pixel group selected by a first scan line, and second pixel group selected by second scan line. A data line is shared by pixel in the first pixel group and a pixel in the second pixel group. In first scanning period, a driving unit in a circuit device outputs a data voltage with first polarity to the first data line, and outputs data voltage with second polarity, which is polarity opposite to the first polarity, to the second data line. In second scanning period, the driving unit outputs a data voltage with third polarity to the first data line, and outputs a data voltage with fourth polarity, which is polarity opposite to the third polarity, to the second data line. A polarity setting unit in the circuit device sets the first polarity, the second polarity, the third polarity, and the fourth polarity.

Abstract: Provided are a control circuit for a switching regulator that can switch off a transistor that drives an inductor at high speed, an integrated circuit device, the switching regulator, an electronic device, and the like. A control circuit (100) includes a signal generation circuit (10) and an output circuit (20). The signal generation circuit (10) generates a control signal (SG) for a switching regulator. Upon receiving the control signal (SG), the output circuit (20) outputs a drive signal (GD) to a gate of an N-type transistor (30) that drives an inductor (40). The output circuit (20) outputs a voltage level lower than a source voltage of the N-type transistor (30) as an off-voltage level of the drive signal (GD) for switching off the N-type transistor (30).

Abstract: A circuit device includes a grayscale voltage generation circuit that generates a plurality of grayscale voltages, a data processing unit that performs data processing of first color component display data to third color component display data, and a drive unit that drives a display panel based on the first color component display data to the third color component display data that are subjected to the data processing and the plurality of grayscale voltages that are used in common for the first color component display data to the third color component display data. The data processing unit performs grayscale correction processing on at least one color component display data of the first color component display data to the third color component display data in a grayscale correction range.

Abstract: A driver includes a power supply circuit having first to n-th boost circuits, a circuit that operates based on power supplied from the power supply circuit, and an abnormality detection circuit. The abnormality detection circuit detects an abnormality of an i-th boosted voltage that is generated based on a boost operation of an i-th boost circuit. If an abnormality of the i-th boosted voltage is detected, a j-th boost circuit performs a low-capacity boost operation with a lower current-supply capacity than an ordinary boost operation or stops the boost operation.

Abstract: An amplification circuit that can reduce an area without using transistors with a high withstand voltage. The amplification circuit (100) includes: an operational amplifier with a first input terminal connected to a reference node; a first capacitor (CA1) provided between a first node and the reference node; a second capacitor (CA2) provided between a second node and the reference node; a switch element (SW1) provided between the first node and an input node of an input voltage; a switch element (SW2) provided between the first node and a supply node of a first analog reference voltage; a switch element (SW3) provided between the second node and an output node of an output voltage; a switch element (SW4) provided between the second node and a supply node of a second analog reference voltage; and a switch element (SW5) provided between the output node of the output voltage and the reference node.

Abstract: Provided are a control circuit for a switching regulator that can switch off a transistor that drives an inductor at high speed, an integrated circuit device, the switching regulator, an electronic device, and the like. A control circuit (100) includes a signal generation circuit (10) and an output circuit (20). The signal generation circuit (10) generates a control signal (SG) for a switching regulator. Upon receiving the control signal (SG), the output circuit (20) outputs a drive signal (GD) to a gate of an N-type transistor (30) that drives an inductor (40). The output circuit (20) outputs a voltage level lower than a source voltage of the N-type transistor (30) as an off-voltage level of the drive signal (GD) for switching off the N-type transistor (30).

Abstract: An amplification circuit that can reduce an area without using transistors with a high withstand voltage. The amplification circuit (100) includes: an operational amplifier with a first input terminal connected to a reference node; a first capacitor (CA1) provided between a first node and the reference node; a second capacitor (CA2) provided between a second node and the reference node; a switch element (SW1) provided between the first node and an input node of an input voltage; a switch element (SW2) provided between the first node and a supply node of a first analog reference voltage; a switch element (SW3) provided between the second node and an output node of an output voltage; a switch element (SW4) provided between the second node and a supply node of a second analog reference voltage; and a switch element (SW5) provided between the output node of the output voltage and the reference node.

Abstract: An integrated circuit device includes first to Nth memory blocks disposed along a first direction, a power supply circuit, and a data driver disposed in a second direction with respect to the first to Nth memory blocks. The power supply circuit includes an analog reference power supply voltage output circuit that outputs an analog reference power supply voltage. The analog reference power supply voltage output circuit is disposed between an Mth memory block and an (M+1)th memory block among the first to Nth memory blocks. An analog reference power supply line is provided in an area of the data driver along the first direction.

Abstract: A D/A conversion circuit includes a first D/A converter and a second D/A converter that respectively output a first voltage and a second voltage. An ith two-input selector among a plurality of input selectors of the first D/A converter selects a (4i+1)th input voltage or a (4i+3)th input voltage based on input data, and outputs the selected input voltage to a selector of a selector block in the subsequent stage. An ith three-input selector among a plurality of three-input selectors of the second D/A converter selects a 4ith input voltage, a (4i+2)th input voltage, or a (4i+4)th input voltage based on the input data, and outputs the selected input voltage to a selector of a selector block in the subsequent stage.

Abstract: A driver circuit for driving source lines of an electro-optical device includes first and second source short-circuit circuits that respectively short-circuit first and second source lines and a source short-circuit node, a source charge storage short-circuit circuit that short-circuits a source charge storage node connected with one end of a source capacitor and the source short-circuit node, a voltage setting circuit that supplies a given voltage to the source charge storage node, and a node short-circuit circuit that short-circuits a common electrode voltage output node and the source short-circuit node, a voltage output to a common electrode of the electro-optical device provided opposite to a pixel electrode through an electro-optical element being applied to the common electrode voltage output node.

Abstract: An integrated circuit device includes a plurality of data line driver circuits, a first correction D/A conversion circuit, and a plurality of D/A conversion circuits. Each of the data line driver circuits includes an operational amplifier, an input capacitor, and a first correction capacitor. Each of the D/A conversion circuits outputs an output signal to the input capacitor. The first correction D/A conversion circuit outputs a correction output voltage to the first correction capacitors to correct data signals output from the data line driver circuits.

Abstract: A display driver includes a common electrode charge storage switch provided between a first capacitor element connection node to which one end of a first capacitor element can be connected and a common electrode voltage output node to which a voltage of a common electrode opposite to a pixel electrode of an electro-optical device through an electro-optical material is supplied, a source charge storage switch provided between a second capacitor element connection node to which one end of a second capacitor element can be connected and a source voltage output node to which a voltage of a source line of the electro-optical device is supplied, and a node short circuit switch provided between the common electrode voltage output node and the source voltage output node.

Abstract: An integrated circuit device includes a plurality of data line driver circuits, a first correction D/A conversion circuit, and a plurality of D/A conversion circuits. Each of the data line driver circuits includes an operational amplifier, an input capacitor, and a first correction capacitor. Each of the D/A conversion circuits outputs an output signal to the input capacitor. The first correction D/A conversion circuit outputs a correction output voltage to the first correction capacitors to correct data signals output from the data line driver circuits.

Abstract: An integrated circuit device includes: a grayscale voltage generation circuit that outputs a plurality of grayscale voltages; and a plurality of driver circuits that drive a plurality of data lines upon receiving the plurality of grayscale voltages, wherein the grayscale voltage generation circuit voltage-divides between a high voltage side power supply voltage and a ground voltage thereby generating the plurality of grayscale voltages, each of the plurality of driver circuits includes a data line driving circuit having a first capacitor and a second capacitor, wherein the data line driving circuit performs an inversion-amplification of a gain according to a capacitor ratio between the first capacitor and the second capacitor, thereby outputting data voltages in an output range whose lower limit voltage is higher than the ground voltage.

Abstract: A decoder circuit comprises: first decoder section that decodes an m-bit address signal portion of an (m+n)-bit address signal; and a second decoder section that decodes an n-bit address signal portion of the (m+n)-bit address signal, the first decoder section including a first AND operation circuit section that outputs signals that indicate a decoding result of the m-bit address signal portion, and a second AND operation circuit section that outputs signals that indicate a decoding result of part of the m-bit address signal portion, and the second decoder section including a third AND operation circuit section that outputs signals that indicate a decoding result of the n-bit address signal portion, and a fourth AND operation circuit section that outputs signals that indicate a decoding result of part of the n-bit address signal portion.

Abstract: A semiconductor device includes a P-substrate, an N-well disposed in the P-substrate, an NMOS transistor disposed in the P-substrate and having one of a source and a drain connected to a ground voltage, a P-tap disposed in the P-substrate and connected to a low voltage so as to provide the P-substrate with the low voltage to be lower than the ground voltage, a PMOS transistor disposed in the N-well and having a source connected to a power supply voltage, an N-tap disposed in the N-well and connected to the power supply voltage so as to provide the N-well with the power supply voltage, and a depression-type PMOS transistor having a drain connected to the low voltage and a source connected to the ground voltage so as to prevent a parasitic transistor, which may exist among the PMOS transistor, the N-well, the NMOS transistor, and the P-substrate, from causing a latchup between the power supply voltage and the ground voltage due to the low voltage rising higher than the ground voltage, and for becoming in a cond

Abstract: A decoder circuit comprises: first decoder section that decodes an m-bit address signal portion of an (m+n)-bit address signal; and a second decoder section that decodes an n-bit address signal portion of the (m+n)-bit address signal, the first decoder section including a first AND operation circuit section that outputs signals that indicate a decoding result of the m-bit address signal portion, and a second AND operation circuit section that outputs signals that indicate a decoding result of part of the m-bit address signal portion, and the second decoder section including a third AND operation circuit section that outputs signals that indicate a decoding result of the n-bit address signal portion, and a fourth AND operation circuit section that outputs signals that indicate a decoding result of part of the n-bit address signal portion.

Abstract: An integrated circuit device includes first to Nth memory blocks that are disposed along a first direction, and first to Nth data driver blocks that are disposed along the first direction in a second direction with respect to the first to Nth memory blocks. A Jth memory block among the first to Nth memory blocks dot-sequentially reads subpixel image data and outputs the subpixel image data to a corresponding Jth data driver block among the first to Nth data driver blocks, the subpixel image data being image data corresponding to at least one subpixel. The Jth data driver block receives the subpixel image data from the Jth memory block, and outputs a data signal corresponding to the subpixel image data.