Abstract: An integrated circuit device includes first to Nth data driver blocks that are disposed along a first direction. Each of the first to Nth data driver blocks includes first to Mth sub-driver blocks. Each of the sub-driver blocks includes a D/A conversion circuit that receives image data and D/A-converts the image data, and first to Lth data line driver circuits that are disposed along the first direction in a second direction with respect to the D/A conversion circuit and share the D/A conversion circuit.

Abstract: An integrated circuit device includes first to Nth memory blocks disposed along a first direction, a power supply circuit, and a data driver disposed in a second direction with respect to the first to Nth memory blocks. The power supply circuit includes an analog reference power supply voltage output circuit that outputs an analog reference power supply voltage. The analog reference power supply voltage output circuit is disposed between an Mth memory block and an (M+1)th memory block among the first to Nth memory blocks.

Abstract: A D/A conversion circuit includes a first D/A converter and a second D/A converter that respectively output a first voltage and a second voltage. An ith two-input selector among a plurality of input selectors of the first D/A converter selects a (4i+1)th input voltage or a (4i+3)th input voltage based on input data, and outputs the selected input voltage to a selector of a selector block in the subsequent stage. An ith three-input selector among a plurality of three-input selectors of the second D/A converter selects a 4ith input voltage, a (4i+2)th input voltage, or a (4i+4)th input voltage based on the input data, and outputs the selected input voltage to a selector of a selector block in the subsequent stage.

Abstract: A driver circuit includes a first capacitor provided between a first node and a reference node, a second capacitor provided between a second node and the reference node, a first switch element provided between the first node and an input node, a second switch element provided between the first node and an analog reference power supply, a third switch element provided between the second node and an output node, a fourth switch element provided between the second node and the analog reference power supply, and a fifth switch element provided between the output node and the reference node. A first capacitor area and a second capacitor area are disposed along a first direction. The first switch element and the second switch element are disposed in a third direction with respect to the first capacitor area and the second capacitor area. The third switch element and the fourth switch element are disposed in the first direction with respect to the first capacitor area and the second capacitor area.

Abstract: A data driver includes a D/A conversion circuit, a switch circuit, and a data line driver circuit. The switch circuit includes a first switch element provided between a first voltage output node of the D/A conversion circuit and a first input node of a grayscale generation amplifier, a second switch element that is provided between a second voltage output node of the D/A conversion circuit and the first input node and is exclusively turned ON/OFF with respect to the first switch element, a third switch element provided between the first voltage output node and a second input node, and a fourth switch element that is provided between the second voltage output node and the second input node and is exclusively turned ON/OFF with respect to the third switch element.

Abstract: A driver circuit for driving source lines of an electro-optical device includes first and second source short-circuit circuits that respectively short-circuit first and second source lines and a source short-circuit node, a source charge storage short-circuit circuit that short-circuits a source charge storage node connected with one end of a source capacitor and the source short-circuit node, a voltage setting circuit that supplies a given voltage to the source charge storage node, and a node short-circuit circuit that short-circuits a common electrode voltage output node and the source short-circuit node, a voltage output to a common electrode of the electro-optical device provided opposite to a pixel electrode through an electro-optical element being applied to the common electrode voltage output node.

Abstract: A semiconductor device includes a P-substrate, an N-well disposed in the P-substrate, an NMOS transistor disposed in the P-substrate and having one of a source and a drain connected to a ground voltage, a P-tap disposed in the P-substrate and connected to a low voltage so as to provide the P-substrate with the low voltage to be lower than the ground voltage, a PMOS transistor disposed in the N-well and having a source connected to a power supply voltage, an N-tap disposed in the N-well and connected to the power supply voltage so as to provide the N-well with the power supply voltage, and a depression-type PMOS transistor having a drain connected to the low voltage and a source connected to the ground voltage so as to prevent a parasitic transistor, which may exist among the PMOS transistor, the N-well, the NMOS transistor, and the P-substrate, from causing a latchup between the power supply voltage and the ground voltage due to the low voltage rising higher than the ground voltage, and for becoming in a cond

Abstract: A gate driver includes a first gate output circuit which outputs a select signal for selecting the first gate line, a second gate output circuit which outputs a select signal for selecting the second gate line in a select period subsequent to the select period of the first gate line, and a transistor as a first gate line short-circuiting circuit provided between outputs of the first and second gate output circuits. The transistor short-circuits the outputs of the first and second gate output circuits in a period between the select period of the first gate line and the select period of the second gate line.

Abstract: A display driver includes a common electrode charge storage switch provided between a first capacitor element connection node to which one end of a first capacitor element can be connected and a common electrode voltage output node to which a voltage of a common electrode opposite to a pixel electrode of an electro-optical device through an electro-optical material is supplied, a source charge storage switch provided between a second capacitor element connection node to which one end of a second capacitor element can be connected and a source voltage output node to which a voltage of a source line of the electro-optical device is supplied, and a node short circuit switch provided between the common electrode voltage output node and the source voltage output node.

Abstract: To reduce power consumption in an IC driver that is capable of accommodating image data in a plurality of kinds of unit bit lengths and supplies a plurality of display signals to a plurality of corresponding respective electrodes of an image display device based on image data, a semiconductor integrated circuit is equipped with a counter that counts a clock signal and outputs count values, a comparison data generation circuit that outputs a plurality of kinds of comparison data for each kind of unit bit length of image data based on the count values outputted from the counter, a comparison circuit that compares image data in a unit bit length and the comparison data that are successively outputted from the comparison data generation circuit, and a pulse output circuit that determines pulse widths of the plurality of display signals to be supplied to the plurality of corresponding respective electrodes based on a comparison result obtained by the comparison circuit and outputs the display signals.

Abstract: A charge-pump circuit includes: MOS transistors connected in series and having one end to which a system ground power supply voltage is supplied; and a discharge transistor. The discharge transistor has one end connected to a node which is connected to the MOS transistors, and the system ground power supply voltage is supplied to the other end of the discharge transistor. The MOS transistors are implemented by a triple-well structure formed in a p-type semiconductor substrate. When a normal operation is performed, the MOS transistors are turned ON and the discharge transistor is turned OFF. When a discharge operation is performed, the MOS transistors are turned OFF and the discharge transistor is turned ON, and a current path is formed by parasitic bipolar transistor elements.

Abstract: A power source circuit includes a power source wiring at a high potential side provided with a first power source voltage and a second power source voltage, a power source wiring at a low potential side and booster circuit as a charge pump installed between the power source wiring at a high potential side and the power source wiring at a low potential side and provided with a plurality of switching transistors and a plurality of capacitors. A control device is provided for controlling the booster circuit. A predetermined number of power sources includes the power source wiring at the high potential side are further provided with the power source circuit. An input voltage is selectively input to a part of the booster circuit from any one of the predetermined number of power sources.

Abstract: A charge-pump circuit includes: MOS transistors connected in series and having one end to which a system ground power supply voltage is supplied; and a discharge transistor. The discharge transistor has one end connected to a node which is connected to the MOS transistors, and the system ground power supply voltage is supplied to the other end of the discharge transistor. The MOS transistors are implemented by a triple-well structure formed in a p-type semiconductor substrate. When a normal operation is performed, the MOS transistors are turned ON and the discharge transistor is turned OFF. When a discharge operation is performed, the MOS transistors are turned OFF and the discharge transistor is turned ON, and a current path is formed by parasitic bipolar transistor elements.

Abstract: A charge-pump circuit includes: MOS transistors connected in series and having one end to which a system ground power supply voltage is supplied; and first to fifth discharge transistors having one end connected to the system ground power supply voltage and the other end connected to the MOS transistors. The MOS transistors are implemented by a triple-well structure formed in a p-type semiconductor substrate. When a discharge operation is performed, the first to fifth discharge transistors are separately ON/OFF controlled, thereby preventing parasitic bipolar transistor elements from being Darlington-connected and preventing a current path from being formed.

Abstract: To reduce power consumption in an IC driver that is capable of accommodating image data in a plurality of kinds of unit bit lengths and supplies a plurality of display signals to a plurality of corresponding respective electrodes of an image display device based on image data, a semiconductor integrated circuit is equipped with a counter that counts a clock signal and outputs count values, a comparison data generation circuit that outputs a plurality of kinds of comparison data for each kind of unit bit length of image data based on the count values outputted from the counter, a comparison circuit that compares image data in a unit bit length and the comparison data that are successively outputted from the comparison data generation circuit, and a pulse output circuit that determines pulse widths of the plurality of display signals to be supplied to the plurality of corresponding respective electrodes based on a comparison result obtained by the comparison circuit and outputs the display signals.

Abstract: A power source circuit includes a power source wiring at a high potential side provided with a first power source voltage and a second power source voltage, a power source wiring at a low potential side and booster circuit as a charge pump installed between the power source wiring at a high potential side and the power source wiring at a low potential side and provided with a plurality of switching transistors and a plurality of capacitors. A control device is provided for controlling the booster circuit. A predetermined number of power sources includes the power source wiring at the high potential side are further provided with the power source circuit. An input voltage is selectively input to a part of the booster circuit from any one of the predetermined number of power sources.