Patents by Inventor Motohito Hori
Motohito Hori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11251163Abstract: A semiconductor device having a semiconductor module that includes a first conductor layer and a second conductor layer facing each other, a group of semiconductor elements that are formed between the first and second conductor layers, and are connected to the second conductor layer respectively via a group of conductor blocks, and a circuit board having one end portion thereof located in a space between the semiconductor elements and the second conductor layer. Each semiconductor element includes first and second main electrodes respectively formed on first and second main surfaces thereof, and a control electrode that is formed on the second main surface. The first main electrode is electrically connected to the first conductor layer. The second main electrode is electrically connected to the second conductor layer via the respective conductor block. The circuit board includes a first wiring layer electrically connected to the control electrodes of the semiconductor elements.Type: GrantFiled: October 29, 2020Date of Patent: February 15, 2022Assignee: FUJI ELECTRIC CO., LTD.Inventors: Motohito Hori, Yoshinari Ikeda, Akira Hirao
-
Patent number: 11189608Abstract: A semiconductor device includes circuit substrates 3 and 9 including circuit pattern layers 3c/9b, a semiconductor element 5 mounted to the circuit pattern layer 3c, a connecting pin 7 connecting the semiconductor element 5 to the circuit pattern layer 9b, a pin-shaped terminal 17 connected to the circuit pattern layer 9b, a sealing member 2 sealing the circuit substrates 3 and 9, the semiconductor element 5, and the connecting pin 7, and an external terminal 27 including a flat plate portion 27s and an extending portion 27t bent from the flat plate portion 27s and extends away from the circuit substrate 9, in which the flat plate portion 27s is connected to the pin-shaped terminal 17 and arranged in parallel with the circuit pattern layer 9b, and the extending portion 27t is provided in a range of a width in a transverse direction of the sealing member 2.Type: GrantFiled: February 25, 2020Date of Patent: November 30, 2021Assignee: FUJI ELECTRIC CO., LTD.Inventors: Hideyo Nakamura, Motohito Hori, Yuki Inaba
-
Publication number: 20210242103Abstract: A semiconductor module includes a laminated substrate having an insulating plate, a circuit pattern on an upper surface of the insulating plate and a heat dissipating plate on a lower surface of the insulating plate. The module further includes a semiconductor device having upper and lower surfaces, and including a collector electrode on the device upper surface, an emitter electrode and a gate electrode on the device lower surface, and the emitter electrode and the gate electrode each being bonded to an upper surface of the circuit pattern via a bump, and a block electrode bonded to the collector electrode. The block electrode includes a flat plate portion covering over the semiconductor device, and a pair of projecting portions projecting toward the circuit pattern from both ends of the flat plate portion in a thickness direction orthogonal to a surface of the insulating plate, and being bonded to the circuit pattern.Type: ApplicationFiled: January 5, 2021Publication date: August 5, 2021Applicant: FUJI ELECTRIC CO., LTD.Inventors: Ryoichi KATO, Yoshinari IKEDA, Tatsuo NISHIZAWA, Motohito HORI, Eiji MOCHIZUKI
-
Publication number: 20210193628Abstract: A semiconductor device having a semiconductor module that includes a first conductor layer and a second conductor layer facing each other, a group of semiconductor elements that are formed between the first and second conductor layers, and are connected to the second conductor layer respectively via a group of conductor blocks, and a circuit board having one end portion thereof located in a space between the semiconductor elements and the second conductor layer. Each semiconductor element includes first and second main electrodes respectively formed on first and second main surfaces thereof, and a control electrode that is formed on the second main surface. The first main electrode is electrically connected to the first conductor layer. The second main electrode is electrically connected to the second conductor layer via the respective conductor block. The circuit board includes a first wiring layer electrically connected to the control electrodes of the semiconductor elements.Type: ApplicationFiled: October 29, 2020Publication date: June 24, 2021Applicant: FUJI ELECTRIC CO., LTD.Inventors: Motohito HORI, Yoshinari IKEDA, Akira HIRAO
-
Publication number: 20210184023Abstract: A semiconductor device having a semiconductor module. The semiconductor module includes first and second conductor layers facing each other, a first semiconductor element provided between the first and second conductor layers, positive and negative electrode terminals respectively provided on edge portions of the first and second conductor layers at a first side of the semiconductor module in a top view of the semiconductor module, control wiring that is electrically connected to the first control electrode, and that extends out of the first and second conductor layers at a second side of the semiconductor module that is opposite to the first side in the top view, and a control terminal that is electrically connected to the control wiring, that is positioned outside the first and second conductor layers in the top view, and that has an end portion that is aligned with the positive and negative electrode terminals.Type: ApplicationFiled: October 30, 2020Publication date: June 17, 2021Applicant: FUJI ELECTRIC CO., LTD.Inventors: Motohito HORI, Yoshinari IKEDA, Akira HIRAO, Tsunehiro NAKAJIMA
-
Publication number: 20210125916Abstract: A semiconductor module, including a board that has first and second conductive plates located side by side on a first insulating plate, a first external connection terminal located on the first conductive plate, first and second semiconductor chips respectively disposed on the first and second conductive plates, and a printed-circuit board including a second insulating plate and first and second wiring boards located on a first principal plane of the second insulating plate. The first wiring board electrically connects an upper surface electrode of the first semiconductor chip and a relay area on the second conductive plate. The second wiring board is electrically connected to an upper surface electrode of the second semiconductor chip. The semiconductor module further includes a second external connection terminal electrically connected to an end portion of the second wiring board and formed on the second principal plane of the second insulating plate.Type: ApplicationFiled: October 23, 2020Publication date: April 29, 2021Applicant: FUJI ELECTRIC CO., LTD.Inventors: Akira HIRAO, Yoshinari IKEDA, Motohito HORI
-
Publication number: 20210104499Abstract: A semiconductor module having a first metal wiring board, a second metal wiring board, a third metal wiring board, and a first semiconductor element and a second semiconductor element that each include an emitter electrode and a collector electrode. The second metal wiring board is disposed over a principal surface of the first metal wiring board with an insulation material therebetween. The third metal wiring board has a principal surface thereof facing the first metal wiring board. The first and second semiconductor elements are disposed to face directions opposite to each other. The collector electrodes of the first and second semiconductor elements respectively face the principal surfaces of the first and third metal wiring boards. The emitter electrodes of the first and second semiconductor elements are respectively connected to the principal surfaces of the third and second metal wiring boards.Type: ApplicationFiled: September 25, 2020Publication date: April 8, 2021Applicant: FUJI ELECTRIC CO., LTD.Inventors: Motohito HORI, Yoshinari IKEDA
-
Patent number: 10867980Abstract: Semiconductor equipment includes semiconductor modules sealed with a resin, each having first and second connection terminals exposed from the resin, a capacitor including third and fourth connection terminals, a cooler directly contacting the semiconductor modules and the capacitor, a busbar including a first busbar connecting the first connection terminal to the third connection terminal, a second busbar connecting the second connection terminal to the fourth connection terminal, and a first insulating layer sandwiched by the first and second busbars, main surfaces of the first and second busbars being parallel to each other, a control circuit board configured to control the semiconductor modules, and a heat transfer component including a main body connected to the cooler, and a second insulating layer arranged on the main body, the main body being in contact with the busbar and the control circuit via the second insulating layer.Type: GrantFiled: October 1, 2019Date of Patent: December 15, 2020Assignee: FUJI ELECTRIC CO., LTD.Inventors: Motohito Hori, Yoshinari Ikeda, Akira Hirao, Mai Saitou, Ryoichi Kato
-
Publication number: 20200194415Abstract: A semiconductor device includes circuit substrates 3 and 9 including circuit pattern layers 3c/9b, a semiconductor element 5 mounted to the circuit pattern layer 3c, a connecting pin 7 connecting the semiconductor element 5 to the circuit pattern layer 9b, a pin-shaped terminal 17 connected to the circuit pattern layer 9b, a sealing member 2 sealing the circuit substrates 3 and 9, the semiconductor element 5, and the connecting pin 7, and an external terminal 27 including a flat plate portion 27s and an extending portion 27t bent from the flat plate portion 27s and extends away from the circuit substrate 9, in which the flat plate portion 27s is connected to the pin-shaped terminal 17 and arranged in parallel with the circuit pattern layer 9b, and the extending portion 27t is provided in a range of a width in a transverse direction of the sealing member 2.Type: ApplicationFiled: February 25, 2020Publication date: June 18, 2020Inventors: Hideyo NAKAMURA, Motohito HORI, Yuki INABA
-
Patent number: 10636740Abstract: A semiconductor device includes a base plate, a plurality of semiconductor units provided in parallel on the base plate, the plurality of semiconductor units implementing a pair, each semiconductor unit including a semiconductor chip and a rod-shaped unit-side control terminal, the unit-side control terminal being connected to the semiconductor chip, the unit-side control terminal extending opposite to the base plate; and an interface unit including a box-shaped accommodating portion, the accommodating portion being provided on the plurality of semiconductor units, the accommodating portion including an internal wiring and a rod-shaped external-connecting control terminal, the internal wiring being connected to each of the plurality of the unit-side control terminals extending from the plurality of semiconductor units, the external-connecting control terminal extending to the outside opposite to the semiconductor units, the external-connecting control terminal being connected to the internal wiring.Type: GrantFiled: March 23, 2018Date of Patent: April 28, 2020Assignees: FUJI ELECTRIC CO., LTD., KOJIN CO., LTD.Inventors: Motohito Hori, Yuki Inaba, Yoshinari Ikeda, Tetsuya Sunago, Michihiro Inaba
-
Publication number: 20200118986Abstract: Semiconductor equipment includes semiconductor modules sealed with a resin, each having first and second connection terminals exposed from the resin, a capacitor including third and fourth connection terminals, a cooler directly contacting the semiconductor modules and the capacitor, a busbar including a first busbar connecting the first connection terminal to the third connection terminal, a second busbar connecting the second connection terminal to the fourth connection terminal, and a first insulating layer sandwiched by the first and second busbars, main surfaces of the first and second busbars being parallel to each other, a control circuit board configured to control the semiconductor modules, and a heat transfer component including a main body connected to the cooler, and a second insulating layer arranged on the main body, the main body being in contact with the busbar and the control circuit via the second insulating layer.Type: ApplicationFiled: October 1, 2019Publication date: April 16, 2020Applicant: FUJI ELECTRIC CO., LTD.Inventors: Motohito HORI, Yoshinari IKEDA, Akira HIRAO, Mai SAITOU, Ryoichi KATO
-
Patent number: 10529642Abstract: The semiconductor device includes a first conductive layer, semiconductor elements bonded to the upper surface of the first conductive layer, a second conductive layer separated from the first conductive layer, a control terminal bonded to the second conductive layer, a control resistor bonded to the upper surface of the second conductive layer, a control-resistor pin bonded to the upper surface of the control resistor and a wiring board having a control-wiring layer for electrically connecting the semiconductor elements and the control-resistor pin.Type: GrantFiled: September 25, 2018Date of Patent: January 7, 2020Assignee: FUJI ELECTRIC CO., LTD.Inventors: Katsumi Taniguchi, Motohito Hori
-
Patent number: 10418359Abstract: A semiconductor device 100 includes a semiconductor element 12 having an electrode on a front surface, a wire 15 bonded to the electrode of the semiconductor element 12, a resin layer 22b covering a bonding portion of the wire 15 on the front surface of the semiconductor element 12, and a gel filler material 23 that seals the semiconductor element 12, the wire 15, and the resin layer 22b. By protecting the bonding portion of the wire 15 with the resin layer 22b, degradation of the wire 15 is ameliorated and the reliability of the semiconductor device 100 is improved.Type: GrantFiled: December 26, 2016Date of Patent: September 17, 2019Assignee: FUJI ELECTRIC CO., LTD.Inventors: Naoyuki Kanai, Motohito Hori, Satoshi Kaneko
-
Publication number: 20190148258Abstract: The semiconductor device includes a first conductive layer, semiconductor elements bonded to the upper surface of the first conductive layer, a second conductive layer separated from the first conductive layer, a control terminal bonded to the second conductive layer, a control resistor bonded to the upper surface of the second conductive layer, a control-resistor pin bonded to the upper surface of the control resistor and a wiring board having a control-wiring layer for electrically connecting the semiconductor elements and the control-resistor pin.Type: ApplicationFiled: September 25, 2018Publication date: May 16, 2019Applicant: Fuji Electric Co., Ltd.Inventors: Katsumi Taniguchi, Motohito Hori
-
Patent number: 10128166Abstract: A power semiconductor module includes a cooler; a plurality of power semiconductor units fixed on the cooler; and a bus bar unit connected electrically to the plurality of power semiconductor units. Each of the plurality of power semiconductor units includes a multilayered substrate including a circuit plate, an insulating plate, and a metal plate laminated in respective order; a semiconductor element fixed to the circuit plate; a wiring member having a printed circuit board and a plurality of conductive posts; external terminals connected electrically and mechanically to the circuit plate; and an insulating sealing material. The bus bar unit includes a plurality of bus bars mutually connecting the external terminals of the plurality of power semiconductor units.Type: GrantFiled: August 8, 2016Date of Patent: November 13, 2018Assignee: FUJI ELECTRIC CO., LTD.Inventors: Motohito Hori, Yoshikazu Takahashi, Eiji Mochizuki, Yoshitaka Nishimura, Yoshinari Ikeda
-
Publication number: 20180294208Abstract: A semiconductor device includes a base plate, a plurality of semiconductor units provided in parallel on the base plate, the plurality of semiconductor units implementing a pair, each semiconductor unit including a semiconductor chip and a rod-shaped unit-side control terminal, the unit-side control terminal being connected to the semiconductor chip, the unit-side control terminal extending opposite to the base plate; and an interface unit including a box-shaped accommodating portion, the accommodating portion being provided on the plurality of semiconductor units, the accommodating portion including an internal wiring and a rod-shaped external-connecting control terminal, the internal wiring being connected to each of the plurality of the unit-side control terminals extending from the plurality of semiconductor units, the external-connecting control terminal extending to the outside opposite to the semiconductor units, the external-connecting control terminal being connected to the internal wiring.Type: ApplicationFiled: March 23, 2018Publication date: October 11, 2018Applicants: FUJI ELECTRIC CO., LTD., KOJIN Co., Ltd.Inventors: Motohito HORI, Yuki INABA, Yoshinari IKEDA, Tetsuya SUNAGO, Michihiro INABA
-
Patent number: 10026665Abstract: For a purpose of raising the breakdown voltage of a semiconductor device, the creepage distance and clearance between an electrode terminal and another metallic portion are preferably increased. A semiconductor device is provided, the semiconductor device including: a semiconductor element; a case portion that houses the semiconductor element; and an external terminal provided to a front surface of the case portion, wherein the front surface of the case portion has, formed thereon: a wall portion that protrudes from the front surface; and a hollow portion that is provided to a region surrounded by the wall portion and is depressed relative to the front surface, and the external terminal is arranged on a floor surface of the hollow portion.Type: GrantFiled: July 26, 2016Date of Patent: July 17, 2018Assignee: FUJI ELECTRIC CO., LTD.Inventors: Motohito Hori, Yoshinari Ikeda
-
Patent number: 9999146Abstract: A semiconductor module includes sealing resin from which a main terminal protrudes, which seals an insulating substrate. The module includes a semiconductor element and a wiring substrate. The sealing resin has a nut housing portion in which a nut is disposed. The semiconductor module also has a busbar terminal to which a main terminal that protrudes from the sealing resin is electrically connected and which has an insertion hole facing the nut.Type: GrantFiled: October 27, 2016Date of Patent: June 12, 2018Assignee: FUJI ELECTRIC CO., LTD.Inventors: Motohito Hori, Yoshinari Ikeda, Hideyo Nakamura, Eiji Mochizuki, Tatsuo Nishizawa
-
Patent number: 9761567Abstract: A power semiconductor module includes a wiring member that electrically connects a front surface electrode of a semiconductor element and a circuit board of an insulating substrate in a housing. A resin provided in the housing covers the wiring member, and has a height in the vicinity of the wiring member. A cover covering the periphery of external terminals is provided between the resin and a first lid in the housing. A second lid is provided further outside the first lid in an aperture portion of the housing, and the space between the second lid and the first lid is filled with another resin.Type: GrantFiled: May 10, 2016Date of Patent: September 12, 2017Assignee: FUJI ELECTRIC CO., LTD.Inventors: Motohito Hori, Yoshinari Ikeda
-
Patent number: D827591Type: GrantFiled: April 20, 2017Date of Patent: September 4, 2018Assignee: FUJI ELECTRIC CO., LTD.Inventors: Yoshinari Ikeda, Motohito Hori, Yuichiro Hinata, Norihiro Daicho