Patents by Inventor Motohito Hori
Motohito Hori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170236819Abstract: A semiconductor device 100 includes a semiconductor element 12 having an electrode on a front surface, a wire 15 bonded to the electrode of the semiconductor element 12, a resin layer 22b covering a bonding portion of the wire 15 on the front surface of the semiconductor element 12, and a gel filler material 23 that seals the semiconductor element 12, the wire 15, and the resin layer 22b. By protecting the bonding portion of the wire 15 with the resin layer 22b, degradation of the wire 15 is ameliorated and the reliability of the semiconductor device 100 is improved.Type: ApplicationFiled: December 26, 2016Publication date: August 17, 2017Inventors: Naoyuki KANAI, Motohito HORI, Satoshi KANEKO
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Publication number: 20170181300Abstract: A semiconductor module includes sealing resin from which a main terminal protrudes, which seals an insulating substrate. The module includes a semiconductor element and a wiring substrate. The sealing resin has a nut housing portion in which a nut is disposed. The semiconductor module also has a busbar terminal to which a main terminal that protrudes from the sealing resin is electrically connected and which has an insertion hole facing the nut.Type: ApplicationFiled: October 27, 2016Publication date: June 22, 2017Applicant: FUJI ELECTRIC CO., LTD.Inventors: Motohito HORI, Yoshinari IKEDA, Hideyo NAKAMURA, Eiji MOCHIZUKI, Tatsuo NISHIZAWA
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Patent number: 9673129Abstract: In a semiconductor device, an insulated substrate is bonded with a cooling body with lowered thermal resistance without a holding unit. The semiconductor device includes an insulated substrate where a wiring pattern copper plate unit for forming a plurality of wiring patterns is disposed on one side of an insulating plate unit, and a heat radiation copper plate unit disposed on the other side of the insulating plate unit; a semiconductor chip mounted on the wiring pattern copper plate unit; a cooling body contacted with the heat radiation copper plate unit; and a wiring conductor plate connected between the semiconductor chip and the wiring pattern copper plate unit. The heat radiation copper plate unit and the cooling body are bonded with a metal sintered material, and thicknesses of the wiring pattern copper plate unit and the heat radiation copper plate unit are set to such thermal stress is relaxed.Type: GrantFiled: September 10, 2015Date of Patent: June 6, 2017Assignee: FUJI ELECTRIC CO., LTD.Inventors: Motohito Hori, Yoshikazu Takahashi, Yoshitaka Nishimura, Yoshinari Ikeda, Hiromichi Gohara
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Publication number: 20170077005Abstract: For a purpose of raising the breakdown voltage of a semiconductor device, the creepage distance and clearance between an electrode terminal and another metallic portion are preferably increased. A semiconductor device is provided, the semiconductor device including: a semiconductor element; a case portion that houses the semiconductor element; and an external terminal provided to a front surface of the case portion, wherein the front surface of the case portion has, formed thereon: a wall portion that protrudes from the front surface; and a hollow portion that is provided to a region surrounded by the wall portion and is depressed relative to the front surface, and the external terminal is arranged on a floor surface of the hollow portion.Type: ApplicationFiled: July 26, 2016Publication date: March 16, 2017Inventors: Motohito HORI, Yoshinari IKEDA
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Patent number: 9524919Abstract: A semiconductor module includes a semiconductor element having a gate electrode and source electrode on the front surface, and a drain electrode on the rear surface, the drain electrode being electrically connected to the front surface of a drain plate; a laminated substrate having, on the front surface of an insulating plate, a first circuit plate to which the gate electrode is electrically connected, and a second circuit plate to which the source electrode is electrically connected, and which is disposed on the front surface of the drain plate; a gate terminal disposed on the first circuit plate; a source terminal disposed on the second circuit plate; and a cover disposed opposite to the front surface of the drain plate, and having an opening in which the gate terminal and the source terminal are positioned and a guide groove contacting the opening and extending to the outer peripheral portion.Type: GrantFiled: March 14, 2016Date of Patent: December 20, 2016Assignee: FUJI ELECTRIC CO., LTD.Inventors: Tetsuya Inaba, Yoshinari Ikeda, Motohito Hori, Daisuke Kimijima
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Publication number: 20160343641Abstract: A power semiconductor module includes a cooler; a plurality of power semiconductor units fixed on the cooler; and a bus bar unit connected electrically to the plurality of power semiconductor units. Each of the plurality of power semiconductor units includes a multilayered substrate including a circuit plate, an insulating plate, and a metal plate laminated in respective order; a semiconductor element fixed to the circuit plate; a wiring member having a printed circuit board and a plurality of conductive posts; external terminals connected electrically and mechanically to the circuit plate; and an insulating sealing material. The bus bar unit includes a plurality of bus bars mutually connecting the external terminals of the plurality of power semiconductor units.Type: ApplicationFiled: August 8, 2016Publication date: November 24, 2016Inventors: Motohito HORI, Yoshikazu TAKAHASHI, Eiji MOCHIZUKI, Yoshitaka NISHIMURA, Yoshinari IKEDA
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Publication number: 20160293517Abstract: A semiconductor module includes a semiconductor element having a gate electrode and source electrode on the front surface, and a drain electrode on the rear surface, the drain electrode being electrically connected to the front surface of a drain plate; a laminated substrate having, on the front surface of an insulating plate, a first circuit plate to which the gate electrode is electrically connected, and a second circuit plate to which the source electrode is electrically connected, and which is disposed on the front surface of the drain plate; a gate terminal disposed on the first circuit plate; a source terminal disposed on the second circuit plate; and a cover disposed opposite to the front surface of the drain plate, and having an opening in which the gate terminal and the source terminal are positioned and a guide groove contacting the opening and extending to the outer peripheral portion.Type: ApplicationFiled: March 14, 2016Publication date: October 6, 2016Inventors: Tetsuya INABA, Yoshinari IKEDA, Motohito HORI, Daisuke KIMIJIMA
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Publication number: 20160254255Abstract: A power semiconductor module includes a wiring member that electrically connects a front surface electrode of a semiconductor element and a circuit board of an insulating substrate in a housing. A resin provided in the housing covers the wiring member, and has a height in the vicinity of the wiring member. A cover covering the periphery of external terminals is provided between the resin and a first lid in the housing. A second lid is provided further outside the first lid in an aperture portion of the housing, and the space between the second lid and the first lid is filled with another resin.Type: ApplicationFiled: May 10, 2016Publication date: September 1, 2016Inventors: Motohito HORI, Yoshinari IKEDA
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Patent number: 9305910Abstract: A semiconductor device includes an insulating substrate having a first conductive pattern on a first insulating substrate; a first semiconductor element having one surface fixed to the first conductive pattern; a printed circuit board having a conductive layer on a second insulating substrate and a plurality of metal pins fixed to the conductive layer; and a third insulating substrate. A portion of pins constituting the metal pins is fixed to other surface of the first semiconductor element, and the printed circuit board with the metal pins is sandwiched between the insulating substrate having the first conductive pattern and the third insulating substrate.Type: GrantFiled: May 7, 2015Date of Patent: April 5, 2016Assignee: FUJI ELECTRIC CO., LTD.Inventors: Masafumi Horio, Kyohei Fukuda, Motohito Hori, Yoshinari Ikeda
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Publication number: 20150380338Abstract: In a semiconductor device, an insulated substrate is bonded with a cooling body with lowered thermal resistance without a holding unit. The semiconductor device includes an insulated substrate where a wiring pattern copper plate unit for forming a plurality of wiring patterns is disposed on one side of an insulating plate unit, and a heat radiation copper plate unit disposed on the other side of the insulating plate unit; a semiconductor chip mounted on the wiring pattern copper plate unit; a cooling body contacted with the heat radiation copper plate unit; and a wiring conductor plate connected between the semiconductor chip and the wiring pattern copper plate unit. The heat radiation copper plate unit and the cooling body are bonded with a metal sintered material, and thicknesses of the wiring pattern copper plate unit and the heat radiation copper plate unit are set to such thermal stress is relaxed.Type: ApplicationFiled: September 10, 2015Publication date: December 31, 2015Inventors: Motohito HORI, Yoshikazu TAKAHASHI, Yoshitaka NISHIMURA, Yoshinari IKEDA, Hiromichi GOHARA
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Patent number: 9209099Abstract: A power semiconductor module is equipped with: a frame made of an insulator; a first electrode plate made of a metal and fixed to a bottom opening of the frame; semiconductor chips electrically and physically connected to the first electrode plate; a multilayer substrate fixed to a principal surface of the first electrode plate; wiring members that electrically connect front surface electrodes of the semiconductor chips and a circuit plate of the multilayer substrate; a second electrode plate fixed to a top opening of the frame; and a metal block that has a first surface having a projected portion and a second surface disposed on a side opposite to the first surface and that is tapered from the first surface to the second surface, the projected portion being electrically and physically connected to the circuit plate of the multilayer substrate and the second surface being electrically and physically connected to the second electrode plate.Type: GrantFiled: April 24, 2015Date of Patent: December 8, 2015Assignee: FUJI ELECTRIC CO., LTD.Inventors: Motohito Hori, Yoshikazu Takahashi, Yoshinari Ikeda
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Publication number: 20150340297Abstract: A power semiconductor module is equipped with: a frame made of an insulator; a first electrode plate made of a metal and fixed to a bottom opening of the frame; semiconductor chips electrically and physically connected to the first electrode plate; a multilayer substrate fixed to a principal surface of the first electrode plate; wiring members that electrically connect front surface electrodes of the semiconductor chips and a circuit plate of the multilayer substrate; a second electrode plate fixed to a top opening of the frame; and a metal block that has a first surface having a projected portion and a second surface disposed on a side opposite to the first surface and that is tapered from the first surface to the second surface, the projected portion being electrically and physically connected to the circuit plate of the multilayer substrate and the second surface being electrically and physically connected to the second electrode plate.Type: ApplicationFiled: April 24, 2015Publication date: November 26, 2015Applicant: Fuji Electric Co., Ltd.Inventors: Motohito HORI, Yoshikazu TAKAHASHI, Yoshinari IKEDA
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Publication number: 20150243640Abstract: A semiconductor device includes an insulating substrate having a first conductive pattern on a first insulating substrate; a first semiconductor element having one surface fixed to the first conductive pattern; a printed circuit board having a conductive layer on a second insulating substrate and a plurality of metal pins fixed to the conductive layer; and a third insulating substrate. A portion of pins constituting the metal pins is fixed to other surface of the first semiconductor element, and the printed circuit board with the metal pins is sandwiched between the insulating substrate having the first conductive pattern and the third insulating substrate.Type: ApplicationFiled: May 7, 2015Publication date: August 27, 2015Inventors: Masafumi HORIO, Kyohei FUKUDA, Motohito HORI, Yoshinari IKEDA
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Patent number: 9059009Abstract: Semiconductor chips are disposed on an insulating substrate with conductive patterns, and a printed circuit board with metal pins is disposed above the insulating substrate with conductive patterns, with the semiconductor chips therebetween. A plurality of external lead terminals is fixed to the insulating substrate with conductive patterns, with the plurality of external lead terminals disposed adjacent to each other in parallel. Furthermore, metal foil pieces formed on front and rear surfaces of the printed circuit board with metal pins respectively so as to face each other, are disposed above the semiconductor chips.Type: GrantFiled: December 25, 2012Date of Patent: June 16, 2015Assignee: FUJI ELECTRIC CO., LTD.Inventors: Masafumi Horio, Kyohei Fukuda, Motohito Hori, Yoshinari Ikeda
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Publication number: 20140346676Abstract: Semiconductor chips are disposed on an insulating substrate with conductive patterns, and a printed circuit board with metal pins is disposed above the insulating substrate with conductive patterns, with the semiconductor chips therebetween. A plurality of external lead terminals is fixed to the insulating substrate with conductive patterns, with the plurality of external lead terminals disposed adjacent to each other in parallel. Furthermore, metal foil pieces, formed on front and rear surfaces of the printed circuit board with metal pins respectively so as to face each other, are disposed above the semiconductor chips.Type: ApplicationFiled: December 25, 2012Publication date: November 27, 2014Applicant: FUJI ELECTRIC CO., LTD.Inventors: Masafumi Horio, Kyohei Fukuda, Motohito Hori, Yoshinari Ikeda
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Patent number: 8836080Abstract: Embodiments of the invention provide a power semiconductor module wherein it is possible to reduce switching noise generated in a switching element, and at the same time, to reduce thermal resistance between a power semiconductor chip and an insulating substrate. In some embodiments, by a capacitor being installed between a printed substrate and an insulating substrate so as to be adjacent to a power semiconductor chip which is a switching element, it is possible to reduce switching noise generated in the switching element, and furthermore, it is possible to reduce thermal resistance between the power semiconductor chip and insulating substrate.Type: GrantFiled: February 13, 2013Date of Patent: September 16, 2014Assignee: Fuji Electric Co., Ltd.Inventors: Motohito Hori, Yoshinari Ikeda, Takafumi Yamada
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Publication number: 20130277800Abstract: Embodiments of the invention provide a power semiconductor module wherein it is possible to reduce switching noise generated in a switching element, and at the same time, to reduce thermal resistance between a power semiconductor chip and an insulating substrate. In some embodiments, by a capacitor being installed between a printed substrate and an insulating substrate so as to be adjacent to a power semiconductor chip which is a switching element, it is possible to reduce switching noise generated in the switching element, and furthermore, it is possible to reduce thermal resistance between the power semiconductor chip and insulating substrate.Type: ApplicationFiled: February 13, 2013Publication date: October 24, 2013Applicant: FUJI ELECTRIC CO., LTD.Inventors: Motohito HORI, Yoshinari IKEDA, Takafumi YAMADA
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Patent number: D689833Type: GrantFiled: November 18, 2011Date of Patent: September 17, 2013Assignee: Fuji Electric Co., Ltd.Inventors: Motohito Hori, Tatsuo Nishizawa, Yoshinari Ikeda, Eiji Mochizuki