Abstract: A method and system for determining the eye pattern margin parameters of a receiver system during diagnostic testing is presented. The circuitry in the receiver's front end comprises a series of latches, XOR gates and OR gates which first provide the data samples and edge samples, i.e., data sampled at the rising or falling edge of an (edge) clock characterized by a phase delay relative to the data sampling clock. The receiver also comprises optimization circuitry for the ideal alignment of the edge clock (edges) with the data edges. The method further provides for a phase shifting of the edge clock to the left and right from the ideal/locked position to screen the data eye pattern in order to compute the Bit Error Rate (BER) value. The position of the edge clock relative to the data sampling clock determines the horizontal eye opening for the computed BER.

Abstract: Techniques are disclosed for fabricating tunable electrical components in integrated circuits. For example, a method of tuning a value of an electrical component, such as a planar inductor, includes the steps of placing a conductive layer in proximity of the electrical component, and adjusting an amount of material that constitutes the conductive layer such that the value of the electrical component is tuned to a particular value. The adjustment step may be performed so as to select a frequency band with which the inductor is associated or to correct a manufacturing deviation in a frequency with which the inductor is associated.

Abstract: Apparatus for use in providing full-rate clock data retiming in a time division multiplexer, wherein the time division multiplexer includes an N to 1 time division multiplexer circuit and a retiming circuit, comprises the following circuitry. The apparatus comprises first circuitry for generating a half-rate clock from a full-rate clock used by the retiming circuit and for providing selective adjustment of a phase associated with the half-rate clock within a range of D degrees. The apparatus further comprises second circuitry, coupled to the first circuitry, for generating a set of sub-rate clocks from the phase-adjustable half-rate clock for use by the N to 1 time division multiplexer circuit in generating a multiplexed data stream from N parallel data streams, such that the retiming circuit is able to operate within a clock phase margin associated therewith. Phase adjustment need not be dependent on a rate associated with the multiplexed data stream, and may be continuous or discrete.

Abstract: In the context of high-speed serial links, data-dependent jitter compensation techniques performed using phase pre-distortion. Broadly contemplated is an expansion of the notion of pre-emphasis beyond conventional amplitude compensation of ISI, whereby phase pre-emphasis for compensating data-dependent jitter (DDJ) is introduced. DDJ can be addressed by exploiting the relationship between the data sequence and the timing deviation. Phase pre-emphasis improves the signal integrity with little additional power consumption in the transmitter and with no cross-talk penalty.

Abstract: Clock synchronization and data recovery techniques are disclosed. For example, a technique for synchronizing a clock for use in recovering received data comprises the following steps/operations. A first clock (e.g., a data clock) is set for a first sampling cycle to a first phase position within a given unit interval in the received data. A second clock (e.g., a sweep clock) is swept through other phase positions with respect to the first phase position such that a transition from the given unit interval to another unit interval in the received data is determined. A sampling point is determined based on measurements at the phase positions associated with the second clock. The second clock is set to the phase position corresponding to the sampling point such that data may be recovered at that sampling point.

Abstract: A phase detector (and method therefor), includes a first flip-flop for sampling an incoming data signal in accordance with a first local clock signal to produce a first sampled data signal, a second flip-flop for sampling the incoming data signal in accordance with a second local clock signal to produce a second sampled data signal, and a third flip-flop for sampling the second sampled data signal, as based on the first sampled data signal, to produce a binary control signal. The third flip-flop comprises a double-edge flip-flop.

Abstract: Apparatus for use in providing full-rate clock data retiming in a time division multiplexer, wherein the time division multiplexer includes an N to 1 time division multiplexer circuit and a retiming circuit, comprises the following circuitry. The apparatus comprises first circuitry for generating a half-rate clock from a full-rate clock used by the retiming circuit and for providing selective adjustment of a phase associated with the half-rate clock within a range of D degrees. The apparatus further comprises second circuitry, coupled to the first circuitry, for generating a set of sub-rate clocks from the phase-adjustable half-rate clock for use by the N to 1 time division multiplexer circuit in generating a multiplexed data stream from N parallel data streams, such that the retiming circuit is able to operate within a clock phase margin associated therewith. Phase adjustment need not be dependent on a rate associated with the multiplexed data stream, and may be continuous or discrete.

Abstract: A phase detector for a clock and data recovery circuit from random non-return-to zero (NRZ) data signal includes a plurality (e.g., preferably three) edge-triggered flip-flops. The incoming NRZ data are sampled by a pair of edge-triggered flip-flops using the transition of the clock generated by the clock recovery circuit. A third edge-triggered flip-flop processes the outputs from the edge-triggered flip-flop pair to indicate whether the generated clock leads or lags the received data.

Abstract: The LC VCO includes an LC oscillator module with first and second tank nodes and a control module with positive and negative input voltage terminals. The control module includes four voltage dependent capacitive elements which are configured to be biased for operation as voltage dependent variable capacitances. The voltage dependent capacitive elements are interconnected such that the effect of a common mode input voltage is to increase the capacitance of two of the voltage dependent capacitive elements, while simultaneously decreasing the capacitance of two of the other voltage dependent capacitive elements by a substantially similar amount, such that a differential voltage applied across the positive and negative input voltage terminals is operable to change the capacitance of the voltage dependent capacitive elements, and thereby the frequency of the LC oscillator module, while effects on the output frequency of the oscillator caused by a common mode voltage tend to cancel.