Patents by Inventor Mrinal K. Das

Mrinal K. Das has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8536066
    Abstract: Methods of forming an oxide layer on silicon carbide include thermally growing an oxide layer on a layer of silicon carbide, and annealing the oxide layer in an environment containing NO at a temperature greater than 1175° C. The oxide layer may be annealed in NO in a silicon carbide tube that may be coated with silicon carbide. To form the oxide layer, a preliminary oxide layer may be thermally grown on a silicon carbide layer in dry O2, and the preliminary oxide layer may be re-oxidized in wet O2.
    Type: Grant
    Filed: May 10, 2010
    Date of Patent: September 17, 2013
    Assignee: Cree, Inc.
    Inventors: Mrinal K. Das, Brett Hull, Sumi Krishnaswami
  • Publication number: 20120228638
    Abstract: Methods of forming silicon carbide power devices are provided. An n? silicon carbide layer is provided on a silicon carbide substrate. A p-type silicon carbide well region is provided on the n? silicon carbide layer. A buried region of p+ silicon carbide is provided on the p-type silicon carbide well region. An n+ region of silicon carbide is provided on the buried region of p+ silicon carbide. A channel region of the power device is adjacent the buried region of p+ silicon carbide and the n+ region of silicon carbide. An n? region is provided on the channel region and a portion of the n? region is removed from the channel region so that a portion of the n? region remains on the channel region to provide a reduction in a surface roughness of the channel region.
    Type: Application
    Filed: May 14, 2012
    Publication date: September 13, 2012
    Inventors: Mrinal K. Das, Michael Laughner
  • Patent number: 8188483
    Abstract: Power devices are provided including a p-type conductivity well region and a buried p+ conductivity region in the p-type conductivity well region. An n+ conductivity region is provided on the buried p+ conductivity region. A channel region of the power device is provided adjacent the buried p+ conductivity region and n+ conductivity region, the channel region of the power device having a root mean square (RMS) surface roughness of less than about 1.0 ?.
    Type: Grant
    Filed: April 16, 2009
    Date of Patent: May 29, 2012
    Assignee: Cree, Inc.
    Inventors: Mrinal K. Das, Michael Laughner
  • Patent number: 8119539
    Abstract: Methods of forming oxide layers on silicon carbide layers are disclosed, including placing a silicon carbide layer in a chamber such as an oxidation furnace tube that is substantially free of metallic impurities, heating an atmosphere of the chamber to a temperature of about 500° C. to about 1300° C., introducing atomic oxygen in the chamber, and flowing the atomic oxygen over a surface of the silicon carbide layer to thereby form an oxide layer on the silicon carbide layer. In some embodiments, introducing atomic includes oxygen providing a source oxide in the chamber and flowing a mixture of nitrogen and oxygen gas over the source oxide. The source oxide may comprise aluminum oxide or another oxide such as manganese oxide. Some methods include forming an oxide layer on a silicon carbide layer and annealing the oxide layer in an atmosphere including atomic oxygen.
    Type: Grant
    Filed: July 14, 2009
    Date of Patent: February 21, 2012
    Assignee: Cree, Inc.
    Inventors: Mrinal K. Das, Anant K. Agarwal, John W. Palmour, Dave Grider
  • Publication number: 20100320477
    Abstract: A process is described for producing silicon carbide crystals having increased minority carrier lifetimes. The process includes the steps of heating and slowly cooling a silicon carbide crystal having a first concentration of minority carrier recombination centers such that the resultant concentration of minority carrier recombination centers is lower than the first concentration.
    Type: Application
    Filed: August 30, 2010
    Publication date: December 23, 2010
    Applicant: CREE, INC.
    Inventors: Calvin H. Carter, JR., Jason R. Jenny, David P. Malta, Hudson M. Hobgood, Valeri F. Tsvetkov, Mrinal K. Das
  • Patent number: 7811943
    Abstract: A process is described for producing silicon carbide crystals having increased minority carrier lifetimes. The process includes the steps of heating and slowly cooling a silicon carbide crystal having a first concentration of minority carrier recombination centers such that the resultant concentration of minority carrier recombination centers is lower than the first concentration.
    Type: Grant
    Filed: February 7, 2005
    Date of Patent: October 12, 2010
    Assignee: Cree, Inc.
    Inventors: Calvin H. Carter, Jr., Jason R. Jenny, David P. Malta, Hudson M. Hobgood, Valeri F. Tsvetkov, Mrinal K. Das
  • Publication number: 20100221924
    Abstract: Methods of forming an oxide layer on silicon carbide include thermally growing an oxide layer on a layer of silicon carbide, and annealing the oxide layer in an environment containing NO at a temperature greater than 1175° C. The oxide layer may be annealed in NO in a silicon carbide tube that may be coated with silicon carbide. To form the oxide layer, a preliminary oxide layer may be thermally grown on a silicon carbide layer in dry O2, and the preliminary oxide layer may be re-oxidized in wet O2.
    Type: Application
    Filed: May 10, 2010
    Publication date: September 2, 2010
    Inventors: Mrinal K. Das, Brett Hull, Sumi Krishnaswami
  • Patent number: 7727904
    Abstract: Methods of forming an oxide layer on silicon carbide include thermally growing an oxide layer on a layer of silicon carbide, and annealing the oxide layer in an environment containing NO at a temperature greater than 1175° C. The oxide layer may be annealed in NO in a silicon carbide tube that may be coated with silicon carbide. To form the oxide layer, a preliminary oxide layer may be thermally grown on a silicon carbide layer in dry O2, and the preliminary oxide layer may be re-oxidized in wet O2.
    Type: Grant
    Filed: July 14, 2006
    Date of Patent: June 1, 2010
    Assignee: Cree, Inc.
    Inventors: Mrinal K. Das, Brett Hull, Sumi Krishnaswami
  • Publication number: 20100009545
    Abstract: Methods of forming oxide layers on silicon carbide layers are disclosed, including placing a silicon carbide layer in a chamber such as an oxidation furnace tube that is substantially free of metallic impurities, heating an atmosphere of the chamber to a temperature of about 500° C. to about 1300° C., introducing atomic oxygen in the chamber, and flowing the atomic oxygen over a surface of the silicon carbide layer to thereby form an oxide layer on the silicon carbide layer. In some embodiments, introducing atomic includes oxygen providing a source oxide in the chamber and flowing a mixture of nitrogen and oxygen gas over the source oxide. The source oxide may comprise aluminum oxide or another oxide such as manganese oxide. Some methods include forming an oxide layer on a silicon carbide layer and annealing the oxide layer in an atmosphere including atomic oxygen.
    Type: Application
    Filed: July 14, 2009
    Publication date: January 14, 2010
    Inventors: Mrinal K. Das, Anant K. Agarwal, John W. Palmour, Dave Grider
  • Patent number: 7615801
    Abstract: High voltage silicon carbide (SiC) devices, for example, thyristors, are provided. A first SiC layer having a first conductivity type is provided on a first surface of a voltage blocking SiC substrate having a second conductivity type. A first region of SiC is provided on the first SiC layer and has the second conductivity type. A second region of SiC is provided in the first SiC layer, has the first conductivity type and is adjacent to the first region of SiC. A second SiC layer having the first conductivity type is provided on a second surface of the voltage blocking SiC substrate. A third region of SiC is provided on the second SiC layer and has the second conductivity type. A fourth region of SiC is provided in the second SiC layer, has the first conductivity type and is adjacent to the third region of SiC. First and second contacts are provided on the first and third regions of SiC, respectively. Related methods of fabricating high voltage SiC devices are also provided.
    Type: Grant
    Filed: June 23, 2005
    Date of Patent: November 10, 2009
    Assignee: Cree, Inc.
    Inventors: Sei-Hyung Ryu, Jason R. Jenny, Mrinal K. Das, Anant K. Agarwal, John W. Palmour, Hudson McDonald Hobgood
  • Publication number: 20090261351
    Abstract: Power devices are provided including a p-type conductivity well region and a buried p+ conductivity region in the p-type conductivity well region. An n+ conductivity region is provided on the buried p+ conductivity region. A channel region of the power device is provided adjacent the buried p+ conductivity region and n+ conductivity region, the channel region of the power device having a root mean square (RMS) surface roughness of less than about 1.0 ?.
    Type: Application
    Filed: April 16, 2009
    Publication date: October 22, 2009
    Inventors: Mrinal K. Das, Michael Laughner
  • Patent number: 7572741
    Abstract: Methods of forming oxide layers on silicon carbide layers are disclosed, including placing a silicon carbide layer in a chamber such as an oxidation furnace tube that is substantially free of metallic impurities, heating an atmosphere of the chamber to a temperature of about 500 ° C. to about 1300 ° C., introducing atomic oxygen in the chamber, and flowing the atomic oxygen over a surface of the silicon carbide layer to thereby form an oxide layer on the silicon carbide layer. In some embodiments, introducing atomic includes oxygen providing a source oxide in the chamber and flowing a mixture of nitrogen and oxygen gas over the source oxide. The source oxide may comprise aluminum oxide or another oxide such as manganese oxide. Some methods include forming an oxide layer on a silicon carbide layer and annealing the oxide layer in an atmosphere including atomic oxygen.
    Type: Grant
    Filed: September 16, 2005
    Date of Patent: August 11, 2009
    Assignee: Cree, Inc.
    Inventors: Mrinal K. Das, Anant K. Agarwal, John W. Palmour, Dave Grider
  • Patent number: 7528040
    Abstract: Methods of forming silicon carbide power devices are provided. An n? silicon carbide layer is provided on a silicon carbide substrate. A p-type silicon carbide well region is provided on the n? silicon carbide layer. A buried region of p+ silicon carbide is provided on the p-type silicon carbide well region. An n+ region of silicon carbide is provided on the buried region of p+ silicon carbide. A channel region of the power device is adjacent the buried region of p+ silicon carbide and the n+ region of silicon carbide. An n? region is provided on the channel region and a portion of the n? region is removed from the channel region so that a portion of the n? region remains on the channel region to provide a reduction in a surface roughness of the channel region.
    Type: Grant
    Filed: May 24, 2005
    Date of Patent: May 5, 2009
    Assignee: Cree, Inc.
    Inventors: Mrinal K. Das, Michael Laughner
  • Publication number: 20090004883
    Abstract: Methods of forming oxide layers on silicon carbide layers are disclosed, including placing a silicon carbide layer in a chamber such as an oxidation furnace tube that is substantially free of metallic impurities, heating an atmosphere of the chamber to a temperature of about 500° C. to about 1300° C., introducing atomic oxygen in the chamber, and flowing the atomic oxygen over a surface of the silicon carbide layer to thereby form an oxide layer on the silicon carbide layer. In some embodiments, introducing atomic includes oxygen providing a source oxide in the chamber and flowing a mixture of nitrogen and oxygen gas over the source oxide. The source oxide may comprise aluminum oxide or another oxide such as manganese oxide. Some methods include forming an oxide layer on a silicon carbide layer and annealing the oxide layer in an atmosphere including atomic oxygen.
    Type: Application
    Filed: September 16, 2005
    Publication date: January 1, 2009
    Inventors: Mrinal K. Das, Anant K. Agarwal, John W. Palmour, Dave Grider
  • Publication number: 20080233285
    Abstract: Methods of forming an oxide layer on silicon carbide include thermally growing an oxide layer on a layer of silicon carbide, and annealing the oxide layer in an environment containing NO at a temperature greater than 1175° C. The oxide layer may be annealed in NO in a silicon carbide tube that may be coated with silicon carbide. To form the oxide layer, a preliminary oxide layer may be thermally grown on a silicon carbide layer in dry O2, and the preliminary oxide layer may be re-oxidized in wet O2.
    Type: Application
    Filed: July 14, 2006
    Publication date: September 25, 2008
    Inventors: Mrinal K. Das, Brett Hull, Sumi Krishnaswami
  • Patent number: 7414268
    Abstract: Silicon carbide high voltage semiconductor devices and methods of fabricating such devices are provided. The devices include a voltage blocking substrate. Insulated gate bipolar transistors are provided that have a voltage blocking substrate. Planar and beveled edge termination may be provided.
    Type: Grant
    Filed: May 18, 2005
    Date of Patent: August 19, 2008
    Assignee: Cree, Inc.
    Inventors: Sei-Hyung Ryu, Jason R. Jenny, Mrinal K. Das, Hudson McDonald Hobgood, Anant K. Agarwal, John W. Palmour
  • Patent number: 7391057
    Abstract: High voltage silicon carbide (SiC) devices, for example, thyristors, are provided. A first SiC layer having a first conductivity type is provided on a first surface of a voltage blocking SiC substrate having a second conductivity type. A first region of SiC is provided on the first SiC layer and has the second conductivity type. A second region of SiC is provided in the first SiC layer. The second region of SiC has the first conductivity type and is adjacent to the first region of SiC. A second SiC layer having the first conductivity type is provided on a second surface, opposite the first surface, of the voltage blocking SiC substrate. First, second and third contacts are provided on the first region of SiC, the second region of SiC and the second SiC layer, respectively. Related methods of fabricating high voltage SiC devices are also provided.
    Type: Grant
    Filed: May 18, 2005
    Date of Patent: June 24, 2008
    Assignee: Cree, Inc.
    Inventors: Sei-Hyung Ryu, Jason R. Jenny, Mrinal K. Das, Hudson McDonald Hobgood, Anant K. Agarwal, John W. Palmour