Abstract: A nanowire transistor is provided that includes a well implant having a local isolation region for insulating a replacement metal gate from a parasitic channel. In addition, the nanowire transistor includes oxidized caps in the extension regions that inhibit parasitic gate-to-source and gate-to-drain capacitances.

Abstract: Systems and methods are directed to an integrated circuit comprising a reduced height M1 metal line formed of an exemplary material with lower mean free path than Copper, for local routing of on-chip circuit elements of the integrated circuit, wherein the height of the reduced height M1 metal line is lower than a minimum allowed or allowable height of a conventional M1 metal line formed of Copper. The exemplary materials for forming the reduced height M1 metal line include Tungsten (W), Molybdenum (Mo), and Ruthenium (Ru), wherein these exemplary materials also exhibit lower capacitance and lower RC delays than Copper, while providing high electromigration reliability.

Abstract: Self-aligned metal cut and via for Back-End-Of-Line (BEOL) processes for semiconductor integrated circuit (IC) fabrication, and related processes and devices, is disclosed. In this manner, mask placement overlay requirements can be relaxed. This relaxation can be multiples of that allowed by conventional BEOL techniques. This is enabled through application of different fill materials for alternating lines in which a conductor will later be placed. With these different fill materials in place, a print cut and via mask is used, with the mask allowed to overlap other adjacent fill lines to that of the desired line. Etching is then applied that is selective to the desired line but not adjacent lines.

Abstract: Nanowire channel structures of continuously stacked nanowires for complementary metal oxide semiconductor (CMOS) devices are disclosed. In one aspect, an exemplary CMOS device includes a nanowire channel structure that includes a plurality of continuously stacked nanowires. Vertically adjacent nanowires are connected at narrow top and bottom end portions of each nanowire. Thus, the nanowire channel structure comprises a plurality of narrow portions that are narrower than a corresponding plurality of central portions. A wrap-around gate material is disposed around the nanowire channel structure, including the plurality of narrow portions, without entirely wrapping around any nanowire therein. The exemplary CMOS device provides, for example, a larger effective channel width and better gate control than a conventional fin field-effect transistor (FET) (FinFET) of a similar footprint. The exemplary CMOS device further provides, for example, a shorter nanowire channel structure than a conventional nanowire FET.

Abstract: Aspects disclosed in the detailed description include nanowire channel structures of continuously stacked heterogeneous nanowires for complementary metal oxide semiconductor (CMOS) devices. Each of the nanowires has a top end portion and a bottom end portion that are narrower than a central portion. Furthermore, vertically adjacent nanowires are interconnected at the narrower top end portions and bottom end portions. This allows for connectivity between stacked nanowires and for having separation areas between vertically adjacent heterogeneous nanowires. Having the separation areas allows for gate material to be disposed over a large area of the heterogeneous nanowires and, therefore, provides strong gate control, a shorter nanowire channel structure, low parallel plate parasitic capacitance, and low parasitic channel capacitance. Having the nanowires be heterogeneous, i.e.

Abstract: A semiconductor device includes a first magnetic tunnel junction (MTJ) device, a second MTJ device, and a top electrode. The first MTJ device includes a barrier layer. The second MTJ device includes the barrier layer. The top electrode is coupled to the first MTJ device and the second MTJ device.

Abstract: A portion of a bulk silicon (Si) is formed into a fin, having a fin base and, on the fin base, an in-process fin. The fin base is doped Si and the in-process fin is silicon germanium (SiGe). The in-process SiGe fin has a source region and a drain region. Boron is in-situ doped into the drain region and into the source region. Optionally, boron is in-situ doped by forming an epi-layer, having boron, on the drain region and on the source region, and drive-in annealing to diffuse boron in the source region and the drain region.

Abstract: A semiconductor device includes a first magnetic tunnel junction (MTJ) device, a second MTJ device, and a top electrode. The first MTJ device includes a barrier layer. The second MTJ device includes the barrier layer. The top electrode is coupled to the first MTJ device and the second MTJ device.

Abstract: A portion of a bulk silicon (Si) is formed into a fin, having a fin base and, on the fin base, an in-process fin. The fin base is doped Si and the in-process fin is silicon germanium (SiGe). The in-process SiGe fin has a source region and a drain region. Boron is in-situ doped into the drain region and into the source region. Optionally, boron is in-situ doped by forming an epi-layer, having boron, on the drain region and on the source region, and drive-in annealing to diffuse boron in the source region and the drain region.

Abstract: An integrated circuit (IC) device may include a first active transistor of a first-type in a first-type region. The first active transistor may have a first-type work function material and a low channel dopant concentration in an active portion of the first active transistor. The IC device may also include a first isolation transistor of the first-type in the first-type region. The second active transistor may have a second-type work function material and the low channel dopant concentration in an active portion of the first isolation transistor. The first isolation transistor may be arranged adjacent to the first active transistor.

Abstract: An integrated circuit (IC) device may include a first active transistor of a first-type in a first-type region. The first active transistor may have a first-type work function material and a low channel dopant concentration in an active portion of the first active transistor. The IC device may also include a first isolation transistor of the first-type in the first-type region. The second active transistor may have a second-type work function material and the low channel dopant concentration in an active portion of the first isolation transistor. The first isolation transistor may be arranged adjacent to the first active transistor.

Abstract: A fin-based structure may include fins on a surface of a semiconductor substrate. Each of the fins may include a doped portion proximate to the surface of the semiconductor substrate. The fin-based structure may also include an isolation layer disposed between the fins and on the surface of the semiconductor substrate. The fin-based structure may also include a recessed isolation liner on sidewalls of the doped portion of the fins. An unlined doped portion of the fins may extend from the recessed isolation liner to an active portion of the fins at a surface of the isolation layer. The isolation layer is disposed on the unlined doped portion of the fins.

Abstract: A fin-type semiconductor device includes a gate structure and a source/drain structure. The fin-type semiconductor device also includes a gate hardmask structure coupled to the gate structure. The gate hardmask structure comprises a first material. The fin-type semiconductor device further includes a source/drain hardmask structure coupled to the source/drain structure. The source/drain hardmask structure comprises a second material.

Abstract: An integrated circuit (IC) device may include a first active transistor of a first-type in a first-type region. The first active transistor may have a first-type work function material and a low channel dopant concentration in an active portion of the first active transistor. The IC device may also include a first isolation transistor of the first-type in the first-type region. The second active transistor may have a second-type work function material and the low channel dopant concentration in an active portion of the first isolation transistor. The first isolation transistor may be arranged adjacent to the first active transistor.

Abstract: Systems and methods are directed to an integrated circuit comprising a reduced height M1 metal line formed of an exemplary material with lower mean free path than Copper, for local routing of on-chip circuit elements of the integrated circuit, wherein the height of the reduced height M1 metal line is lower than a minimum allowed or allowable height of a conventional M1 metal line formed of Copper. The exemplary materials for forming the reduced height M1 metal line include Tungsten (W), Molybdenum (Mo), and Ruthenium (Ru), wherein these exemplary materials also exhibit lower capacitance and lower RC delays than Copper, while providing high electromigration reliability.

Abstract: A semiconductor device includes a first magnetic tunnel junction (MTJ) device, a second MTJ device, and a top electrode. The first MTJ device includes a barrier layer. The second MTJ device includes the barrier layer. The top electrode is coupled to the first MTJ device and the second MTJ device.

Abstract: A fin-based structure may include fins on a surface of a semiconductor substrate. Each of the fins may include a doped portion proximate to the surface of the semiconductor substrate. The fin-based structure may also include an isolation layer disposed between the fins and on the surface of the semiconductor substrate. The fin-based structure may also include a recessed isolation liner on sidewalls of the doped portion of the fins. An unlined doped portion of the fins may extend from the recessed isolation liner to an active potion of the fins at a surface of the isolation layer. The isolation layer is disposed on the unlined doped portion of the fins.

Abstract: A semiconductor device includes a gate stack. The semiconductor device also includes a wrap-around contact arranged around and contacting substantially all surface area of a regrown source/drain region of the semiconductor device proximate to the gate stack.

Abstract: Systems and methods are directed to an integrated circuit comprising a reduced height M1 metal line formed of an exemplary material with lower mean free path than Copper, for local routing of on-chip circuit elements of the integrated circuit, wherein the height of the reduced height M1 metal line is lower than a minimum allowed or allowable height of a conventional M1 metal line formed of Copper. The exemplary materials for forming the reduced height M1 metal line include Tungsten (W), Molybdenum (Mo), and Ruthenium (Ru), wherein these exemplary materials also exhibit lower capacitance and lower RC delays than Copper, while providing high electromigration reliability.

Abstract: The present disclosure provides semiconductor packages and methods for fabricating semiconductor packages. The semiconductor package may comprise a semiconductor device mounted to a first substrate, a voltage regulator mounted to the first substrate and coupled to the semiconductor device, and an inductive element located on a perimeter of the semiconductor device and coupled to the voltage regulator, wherein the inductive element is formed by a plurality of interconnected conductive elements extending vertically from the first substrate.