Abstract: A portion of a bulk silicon (Si) is formed into a fin, having a fin base and, on the fin base, an in-process fin. The fin base is doped Si and the in-process fin is silicon germanium (SiGe). The in-process SiGe fin has a source region and a drain region. Boron is in-situ doped into the drain region and into the source region. Optionally, boron is in-situ doped by forming an epi-layer, having boron, on the drain region and on the source region, and drive-in annealing to diffuse boron in the source region and the drain region.

Abstract: A device includes a first structure and a second structure. The second structure is separated from the first structure by a cavity. The device further includes a seal material, an etch stop material defining an etched region, and a self-aligned contact (SAC). The seal material is configured to seal the cavity, and the SAC is formed within the etched region. The SAC adjoins the seal material, the etch stop material, or a combination thereof.

Abstract: Systems and methods are directed to an integrated circuit comprising a reduced height M1 metal line formed of an exemplary material with lower mean free path than Copper, for local routing of on-chip circuit elements of the integrated circuit, wherein the height of the reduced height M1 metal line is lower than a minimum allowed or allowable height of a conventional M1 metal line formed of Copper. The exemplary materials for forming the reduced height M1 metal line include Tungsten (W), Molybdenum (Mo), and Ruthenium (Ru), wherein these exemplary materials also exhibit lower capacitance and lower RC delays than Copper, while providing high electromigration reliability.

Abstract: In a particular embodiment, a method includes forming a first spacer structure on a dummy gate of a semiconductor device and forming a sacrificial spacer on the first spacer structure. The method also includes etching a structure of the semiconductor device to create an opening, removing the sacrificial spacer via the opening, and depositing a material to close to define a gap.

Abstract: A test circuit and method for testing through-silicon-vias (TSVs) in three-dimensional integrated circuits (ICs) during each phase of manufacturing is disclosed. In one aspect, the method includes testing for faults in each individual TSV, TSV-under-test, shorts between a TSV-under-test, and TSVs in close proximity and for connections between the TSV-under-test and another tier in the ICs. A test circuit has three switchable current paths connected to a power supply via a pull-up resistor and switches: a calibration path, a short path, and a current measurement path. A power supply is connected to the measurement path, and the calibration path and the short path are connected to ground via respective pull-down resistors. For each TSV-under-test, the desired operation mode is selected by the closure of different combinations of switches. The current flowing through the pull-up resistor in each operation mode indicates whether the TSV-under-test has passed or failed the test.

Abstract: A test circuit and method for testing through-silicon-vias (TSVs) in three-dimensional integrated circuits (ICs) during each phase of manufacturing is disclosed. In one aspect, the method includes testing for faults in each individual TSV, TSV-under-test, shorts between a TSV-under-test, and TSVs in close proximity and for connections between the TSV-under-test and another tier in the ICs. A test circuit has three switchable current paths connected to a power supply via a pull-up resistor and switches: a calibration path, a short path, and a current measurement path. A power supply is connected to the measurement path, and the calibration path and the short path are connected to ground via respective pull-down resistors. For each TSV-under-test, the desired operation mode is selected by the closure of different combinations of switches. The current flowing through the pull-up resistor in each operation mode indicates whether the TSV-under-test has passed or failed the test.

Abstract: The disclosure relates to a device comprising at least one delay line for applying a variable delay to a clock signal and a controller for controlling the variable delay of the delay line. Each delay line comprises a plurality of concatenated delay banks which provide different delay values with respect to each other, a bypass parallel over each of said the delay banks, and switching elements associated with each of the delay banks for selecting either the respective delay bank or the respective bypass. Each of the delay banks is provided with a delay bank status indicator for indicating propagation of the clock signal through the delay bank towards the controller. The controller is provided for taking the indicated propagation of the clock signal into account upon setting said switching elements.

Abstract: In one embodiment a method to compensate for the sensitivity drift of a magnetic field sensor for sensing a magnetic field comprises forming a reference magnetic field having first magnetic field parameters, e.g. a first amplitude and/or direction, in a first step and second magnetic field parameters, a second amplitude and/or direction, in a second step and a bias signal is formed without adjusting the bias signal with a feedback signal derived from an output signal of the magnetic field sensor.

Abstract: The present invention provides a method to compensate for the sensitivity drift of a magnetic field sensor for sensing a magnetic field. The magnetic field sensor comprises at least four electrodes. The method comprises a first step where a first set of two electrodes is used to bias the sensor and a second set of two electrodes is used to sense an output signal of the magnetic field sensor, and a second step where the second set of two electrodes is used to bias the sensor and the first set of two electrodes is used to sense an output signal of the magnetic field sensor. The method is characterized in that at least one of the first or the second step is subdivided in at least a first sub-step and a second sub-step. A reference magnetic field has first magnetic field parameters, e.g. a first amplitude and/or direction, in the first sub-step and second magnetic field parameters, a second amplitude and/or direction, in the second sub-step.

Abstract: One inventive aspect relates to a digital sub-circuit suitable for embedding in an at least partially digital circuit for minimizing the influence of another digital sub-circuit on the at least partially digital circuit, the other digital sub-circuit being part of the at least partially digital circuit. The influence of the other digital sub-circuit may, for example, be the introduction of ground bounce by switching of the other digital sub-circuit. Another inventive aspect relates to an at least partially digital circuit comprising such a digital sub-circuit for minimizing the influence of another digital sub-circuit to the at least partially digital circuit and to a method for reducing the influence of another digital sub-circuit to an at least partially digital circuit.

Abstract: A method is presented for determining an actual pulse position in a signal. This signal comprises a plurality of successive frames, wherein each frame has length L and contains one pulse with width W, a number of discrete possible pulse positions being considered within in each frame which is at least L/W. The method comprises the steps of a) sampling the signal at a sampling rate below L/W with a varying sampling phase such that the whole frame length L is covered, b) obtaining a set of samples with at least one at each of the possible pulse positions, c) correlating this set of samples with a set of one or more predetermined values and d) determining the actual pulse position from said correlation. The method provides a low-complex signal acquisition solution in a receiver and is particularly useful for low-complexity and low-power IR-UWB transceivers.

Abstract: The disclosure relates to a device comprising at least one delay line for applying a variable delay to a clock signal and a controller for controlling the variable delay of the delay line. Each delay line comprises a plurality of concatenated delay banks which provide different delay values with respect to each other, a bypass parallel over each of said the delay banks, and switching elements associated with each of the delay banks for selecting either the respective delay bank or the respective bypass. Each of the delay banks is provided with a delay bank status indicator for indicating propagation of the clock signal through the delay bank towards the controller. The controller is provided for taking the indicated propagation of the clock signal into account upon setting said switching elements.

Abstract: The present invention provides a method to compensate for the sensitivity drift of a magnetic field sensor for sensing a magnetic field. The magnetic field sensor comprises at least four electrodes. The method comprises a first step where a first set of two electrodes is used to bias the sensor and a second set of two electrodes is used to sense an output signal of the magnetic field sensor, and a second step where the second set of two electrodes is used to bias the sensor and the first set of two electrodes is used to sense an output signal of the magnetic field sensor. The method is characterized in that at least one of the first or the second step is subdivided in at least a first sub-step and a second sub-step. A reference magnetic field has first magnetic field parameters, e.g. a first amplitude and/or direction, in the first sub-step and second magnetic field parameters, a second amplitude and/or direction, in the second sub-step.

Abstract: A method is presented for determining an actual pulse position in a signal. This signal comprises a plurality of successive frames, wherein each frame has length L and contains one pulse with width W, a number of discrete possible pulse positions being considered within in each frame which is at least L/W. The method comprises the steps of a) sampling the signal at a sampling rate below L/W with a varying sampling phase such that the whole frame length L is covered, b) obtaining a set of samples with at least one at each of the possible pulse positions, c) correlating this set of samples with a set of one or more predetermined values and d) determining the actual pulse position from said correlation. The method provides a low-complex signal acquisition solution in a receiver and is particularly useful for low-complexity and low-power IR-UWB transceivers.

Abstract: One inventive aspect relates to a digital sub-circuit suitable for embedding in an at least partially digital circuit for minimizing the influence of another digital sub-circuit on the at least partially digital circuit, the other digital sub-circuit being part of the at least partially digital circuit. The influence of the other digital sub-circuit may, for example, be the introduction of ground bounce by switching of the other digital sub-circuit. Another inventive aspect relates to an at least partially digital circuit comprising such a digital sub-circuit for minimizing the influence of another digital sub-circuit to the at least partially digital circuit and to a method for reducing the influence of another digital sub-circuit to an at least partially digital circuit.

Abstract: A simulation system is described for computing the overall signal generated in a substrate by a digital system comprising a plurality of gates associated with the substrate, wherein each gate is configured to perform a switching event. Output of a transistor-level model is compared with output of a lumped circuit model for each gate and the substrate, and signal contributions from each gate and switching event are determined based on the comparison. The system determines switching event signals for each of the plurality of gates. The signal contributions and the switching event signals are combined, and a combined lumped circuit model is derived based on a combination of lumped circuit models of the plurality of gates. The overall signal is computed based on the combined gate signal contributions and switching event signals, which are configured as an input to the combined lumped circuit model.

Abstract: A simulation system is described for computing the overall signal generated in a substrate by a digital system comprising a plurality of gates associated with said substrate the overall signal being generated when said digital system would be operational resulting in a plurality of switching events of at least some of said gates. For substantially each of said gates a transistor-level model of said gate and said substrate and a lumped circuit model of said gate and said substrate is loaded on a computer system. Gate and switching event specific signal contributions are determined for each of said switching events by matching said transistor-level model and said lumped circuit model.