Abstract: A system and managing method for cluster-type storage is provided. In one example of the system, the storage system is configured so as to expand from small to large configurations at a reasonable cost with performance decided appropriately to the target system scale. The storage system has an interface with a server or hard drives, a plurality of protocol transformation units, each used for transforming a read or write protocol of the data to be exchanged with the server or hard drives and a plurality of data caching control units, each having a cache memory unit for storing data to be read from or written in the server or hard drives and a function for controlling the cache memory unit. An interconnection is used for the connection between the plurality of the protocol transformation units and the plurality of the data caching control units.

Abstract: Disclosed is a disk control apparatus with excellent scalability realized on the same architecture, in high quality and reliability, regardless of its scale. Each of a plurality of channel interface units and a cache memory unit as well as each of a plurality of disk interface units and the cache memory unit are connected through a switch and a data path network (solid line) in each disk control cluster. Each switch provided outside each disk control cluster is connected to the switch in each disk control cluster through the data path network. A resource management unit is provided outside each disk control cluster and the resource management unit is connected to each of the plurality of channel interface units/disk interface units, as well as to the cache memory unit in each disk control cluster. The resource management unit is also connected to each switch provided outside each disk control cluster through a resource management network (dotted line).

Abstract: A cache access control system for dynamically conducting specification of dedicated and common regions and thereby always conducting optimum cache coherency control. In a processor, an L1 cache including an L1 data array and a directory is provided. A plurality of L2 caches are connected to each L1 cache. The L2 caches are connected to a main memory L3. An L2 cache history manager is supplied with L2 cache status information and an L2 cache access request from L2 caches. The L2 cache history manager judges an attribute (a dedicated region or a common region) of each line of L2. On the basis of the attribute, a cache coherency manager conducts coherency control of each L2 cache by using an invalidation type protocol or an update type protocol. The attribute is judged to be the common region, only in the case where a line shared by a plurality of L2 caches in the past is canceled once by the invalidation type protocol and then accessed again.

Abstract: A cache access control system for dynamically conducting specification of dedicated and common regions and thereby always conducting optimum cache coherency control. In a processor, an L1 cache including an L1 data array and a directory is provided. A plurality of L2 caches are connected to each L1 cache. The L2 caches are connected to a main memory L3. An L2 cache history manager is supplied with L2 cache status information and an L2 cache access request from L2 caches. The L2 cache history manager judges an attribute (a dedicated region or a common region) of each line of L2. On the basis of the attribute, a cache coherency manager conducts coherency control of each L2 cache by using an invalidation type protocol or an update type protocol. The attribute is judged to be the common region, only in the case where a line shared by a plurality of L2 caches in the past is canceled once by the invalidation type protocol and then accessed again.

Abstract: An asynchronous transfer mode switching system for improving switching throughput and averting complicated and difficult timing design. In operation, synchronous cell strings from external transmission lines are converted to asynchronous cell strings which are switched by a space-division switch array. The switched asynchronous cell strings are reconverted to synchronous cell strings for output onto external transmission lines. The space-division switch array comprises a plurality of unit switches in stages, each unit switch having input terminals and output terminals. The unit switches each include a timing control circuit that causes a switching operation to start upon detecting two states concurrently: a stored state of a cell to be switched, and a storage-ready state of a destination for the switched cell. The scheme allows the system to operate in an asynchronous manner.

Abstract: A superconducting logic circuit is configured by using two kinds of input-output type quantum flux parametrons (QFP), that is, a periodically excited input-output type QFP and an arbitrarily excited input-output type QFP. The periodically excited QFP is excited by periodically varying exciting magnetic flux to amplify a binary magnetic flux. The arbitrarily excited QFP is excited by magnetic flux output signals of upstream QFPs.