Abstract: A deposition apparatus is disclosed for depositing a layer on a substrate such as a semiconductor wafer. The deposition apparatus may include a process chamber, and a susceptor in the process chamber with the susceptor being configured to receive a substrate for depositing a thin layer thereon. The deposition apparatus may also include a showerhead on a side of the process chamber with the showerhead being configured to receive reaction gases and to introduce the reaction gases into the process chamber. The showerhead may include a heating element therein for heating reaction gases prior to introducing the reaction gases into the reaction chamber. Related methods are also discussed.

Abstract: Methods for fabricating a contact of a semiconductor device are provided by patterning an interlayer dielectric of the semiconductor device to form a contact hole that exposes a silicon-based region of a first impurity type. The exposed silicon-based region is doped with a gas containing an element of the first impurity type and a contact plug is formed in the contact hole. Contact structure for a semiconductor device are also provided that include an interlayer dielectric of the semiconductor device having a contact hole formed therein that exposes a silicon-based region of a first impurity type. A delta-doped region of the first impurity type is provided in the exposed silicon-based region. A contact plug is provided in the contact hole and on the delta-doped region.

Abstract: A semiconductor device fabrication method having a recess region in an insulation layer on a silicon substrate, includes the steps of depositing a barrier metal on an entire surface of the insulation layer, filling the recess region with an oxide layer, removing the barrier metal on an upper side of the insulation layer, removing the oxide layer in the recess region and exposing the barrier metal of the recess region, depositing a CVD-Al layer on the barrier metal, and depositing a PVD-Al layer on the CVD-Al layer and re-flowing the PVD-Al layer. The fabrication method of a semiconductor integrated circuit according to the present invention selectively removes a barrier metal in the outside of the recess region to expose the insulation layer to the air, and deposits the CVD-Al layer and the PVD-Al layer, which results in controlling abnormal growth of the CVD-Al metal.

Abstract: Forming a semiconductor device can include forming an insulating layer on a semiconductor substrate including a conductive region thereof, wherein the insulating layer has a contact hole therein exposing a portion of the conductive region. A polysilicon contact plug can be formed in the contact hole wherein at least a portion of the polysilicon contact plug is doped with an element having a diffusion coeffient that is less than a diffusion coefficient of phosphorus (P). Related structures are also discussed.

Abstract: An integrated in situ cluster type wafer processing apparatus which can be used for forming metal wiring layers having a multi-layered structure and a wafer processing method using the same are provided. The wafer processing apparatus includes a transfer chamber which can be exhausted and has a plurality of gate valves, a plurality of vacuum processing chambers each of which can be connected to the transfer chamber via one of the gate valves, and a load lock chamber which can be exhausted and is connectable to a first gas feed line for feeding an oxygen-based gas into the load lock chamber. In a wafer processing method, a predetermined layer is formed on a wafer in one of the vacuum processing chambers. The predetermined layer on the wafer is oxidized in the load lock chamber or an oxygen atmosphere chamber.

Abstract: Methods of forming a metal interconnects include forming an electrically insulating layer having a contact hole therein, on a substrate. A step is also performed to form an electrically conductive seed layer. The seed layer extends on a sidewall of the contact hole and on a portion of an upper surface of the electrically insulating layer extending adjacent the contact hole. The seed layer is sufficiently thick along an upper portion of the sidewall and sufficiently thin along a lower portion of the sidewall that an upper portion of the contact hole is partially constricted by the seed layer and a constricted contact hole is thereby defined. An anti-nucleation layer is deposited on a portion of the seed layer that extends outside the constricted contact hole. The constricted contact hole is used as a mask to inhibit deposition of the anti-nucleation layer adjacent a bottom of the constricted contact hole.

Abstract: An integrated in situ cluster type wafer processing apparatus which can be used for forming metal wiring layers having a multi-layered structure and a wafer processing method using the same are provided. The wafer processing apparatus includes a transfer chamber which can be exhausted and has a plurality of gate valves, a plurality of vacuum processing chambers each of which can be connected to the transfer chamber via one of the gate valves, and a load lock chamber which can be exhausted and is connectable to a first gas feed line for feeding an oxygen-based gas into the load lock chamber. In a wafer processing method, a predetermined layer is formed on a wafer in one of the vacuum processing chambers. The predetermined layer on the wafer is oxidized in the load lock chamber or an oxygen atmosphere chamber.

Abstract: A semiconductor device having a contact using a crack-protecting layer and a method of forming the same are provided. The crack-protecting layer formed of a dielectric material is formed on an interlayer dielectric layer. The crack-protecting layer relieves or absorbs residual stress generated on a conductive layer used in forming a contact plug. Thus, a contact can be formed without damage to the interlayer dielectric layer due to residual stress.

Abstract: A heating chamber which can be used during a reflow process to form a metal wiring having a multi-layered writing structure and a method of heating a wafer using the same, are provided. The heating chamber is movable upward and downward between the upper process position and the lower loading position, and includes a pedestal having a supporting surface for supporting a wafer, a cover installed above the pedestal to form a processing area together with the supporting surface when the pedestal is placed in its raised process position and a heating unit for heating the waver. In the method of heating the wafer, the temperature in the processing area is maintained suitable for heating the wafer before the wafer is loaded onto the supporting surface, the wafer is loaded onto the supporting surface and the loaded wafer is heating in the processing area.

Abstract: A method is provided for forming a metal wiring layer of a semiconductor device, which is performed in an airtight space, the pressure of which is maintained below atmospheric pressure, to form a metal deposition prevention layer. An interlayer dielectric layer pattern is formed on a semiconductor substrate so as to define a hole region. A metal film is formed on the top surface of the interlayer dielectric layer pattern under a vacuum state so as to expose the side walls of the hole region. The metal layer is oxidized in the airtight space, the pressure of which is maintained below atmospheric pressure in an oxygen atmosphere, thereby forming a metal deposition prevention layer. A metal liner is selectively formed at the side walls of the hole region. A metal layer is formed inside the hole region defined by the metal liner and on the metal deposition prevention layer. The metal liner is heat-treated and reflowed.

Abstract: An integrated in situ cluster type wafer processing apparatus which can be used for forming metal wiring layers having a multi-layered structure and a wafer processing method using the same are provided. The wafer processing apparatus includes a transfer chamber which can be exhausted and has a plurality of gate valves, a plurality of vacuum processing chambers each of which can be connected to the transfer chamber via one of the gate valves, and a load lock chamber which can be exhausted and is connectable to a first gas feed line for feeding an oxygen-based gas into the load lock chamber. In a wafer processing method, a predetermined layer is formed on a wafer in one of the vacuum processing chambers. The predetermined layer on the wafer is oxidized in the load lock chamber or an oxygen atmosphere chamber.

Abstract: A metal wiring layer of a semiconductor device in which a nucleation liner is formed prior to forming an aluminum liner. A barrier metal layer is formed on a semiconductor substrate. A nucleation liner for growing an aluminum layer is formed on the barrier metal layer in a vacuum state. An aluminum liner is formed by growing an aluminum layer on the nucleation liner using chemical vapor deposition in a vacuum state in situ with the step of forming the nucleation liner. A metal layer is formed on the aluminum liner using physical vapor deposition. The semiconductor substrate is heat-treated and reflowed.

Abstract: A semiconductor device having a contact using a crack-protecting layer and a method of forming the same are provided. The crack-protecting layer formed of a dielectric material is formed on an interlayer dielectric layer. The crack-protecting layer relieves or absorbs residual stress generated on a conductive layer used in forming a contact plug. Thus, a contact can be formed without damage to the interlayer dielectric layer due to residual stress.

Abstract: A method is provided for forming a metal wiring layer of a semiconductor device, which is performed in an airtight space, the pressure of which is maintained below atmospheric pressure, to form a metal deposition prevention layer. An interlayer dielectric layer pattern is formed on a semiconductor substrate so as to define a hole region. A metal film is formed on the top surface of the interlayer dielectric layer pattern under a vacuum state so as to expose the side walls of the hole region. The metal layer is oxidized in the airtight space, the pressure of which is maintained below atmospheric pressure in an oxygen atmosphere, thereby forming a metal deposition prevention layer. A metal liner is selectively formed at the side walls of the hole region. A metal layer is formed inside the hole region defined by the metal liner and on the metal deposition prevention layer. The metal liner is heat-treated and reflowed.

Abstract: A semiconductor device fabrication method having a recess region in an insulation layer on a silicon substrate, includes the steps of depositing a barrier metal on an entire surface of the insulation layer, filling the recess region with an oxide layer, removing the barrier metal on an upper side of the insulation layer, removing the oxide layer in the recess region and exposing the barrier metal of the recess region, depositing a CVD-Al layer on the barrier metal, and depositing a PVD-Al layer on the CVD-Al layer and reflowing the PVD-Al layer. The fabrication method of a semiconductor integrated circuit according to the present invention selectively removes a barrier metal in the outside of the recess region to expose the insulation layer to the air, and deposits the CVD-Al layer and the PVD-Al layer, which results in controlling abnormal growth of the CVD-Al metal.

Abstract: A method of fabricating a semiconductor device having a recess region in an insulation layer on a silicon substrate, comprising the steps of depositing a barrier metal over the entire surface of the insulation layer including the substrate surface in the recess region, depositing selectively an anti-nucleation layer on the barrier metal except in the recess region, depositing a CVD-Al layer on the barrier metal in the recess region, depositing a metal or a metal alloy inhibiting aluminum migration on the barrier metal except in the recess region, and depositing a PVD-Al layer and re-flowing the PVD-Al layer, for improving the quality of aluminum grooves over those generated using conventional PMD-Al processes. The present method inhibits PVD-Al migration and grain growth, which results in preventing abnormal patterning in the semiconductor device.

Abstract: A semiconductor device having a capacitor. The capacitor includes a first electrode, a dielectric layer formed of a metal oxide layer including a Ta2O5 layer, and a second electrode composed of first and second metal nitride layers sequentially stacked. Each of the first and second metal nitride layers has a TiN layer and a WN layer. The second electrode of the capacitor is a double-layered structure having the first and second metal nitride layers, and thus annealing after forming the second electrode is performed at 750° C. or less, to thereby reduce an equivalent oxide thickness of the dielectric layer.

Abstract: Methods of forming a metal interconnects include forming an electrically insulating layer having a contact hole therein, on a substrate. A step is also performed to form an electrically conductive seed layer. The seed layer extends on a sidewall of the contact hole and on a portion of an upper surface of the electrically insulating layer extending adjacent the contact hole. The seed layer is sufficiently thick along an upper portion of the sidewall and sufficiently thin along a lower portion of the sidewall that an upper portion of the contact hole is partially constricted by the seed layer and a constricted contact hole is thereby defined. An anti-nucleation layer is deposited on a portion of the seed layer that extends outside the constricted contact hole. The constricted contact hole is used as a mask to inhibit deposition of the anti-nucleation layer adjacent a bottom of the constricted contact hole.

Abstract: A semiconductor device having a capacitor. The capacitor includes a first electrode, a dielectric layer formed of a metal oxide layer including a Ta2O5 layer, and a second electrode composed of first and second metal nitride layers sequentially stacked. Each of the first and second metal nitride layers has a TiN layer and a WN layer. The second electrode of the capacitor is a double-layered structure having the first and second metal nitride layers, and thus annealing after forming the second electrode is performed at 750° C. or less, to thereby reduce an equivalent oxide thickness of the dielectric layer.

Abstract: The capacitor of semiconductor devices includes a first electrode, a dielectric layer formed of a metal oxide layer including a Ta2O5 layer, and a second electrode composed of first and second metal nitride layers sequentially stacked. First and second metal nitride layers are a TiN layer and a WN layer. The second electrode of the capacitor is a double-layered structure having the first and second metal nitride layers, and thus annealing after forming the second electrode is performed at 750° C. or less to avoid increasing an equivalent oxide thickness of the dielectric layer.