Abstract: In a non-volatile memory controlling device, a first doorbell region is exposed to a configuration space of a host interface and updated when the host issues an input/output (I/O) request command to the host memory. A fetch managing module fetches the command from the host memory in response to an event signal generated when the first doorbell region is updated. A data transferring module checks a location of the host memory based on request information included in the command, and performs a transfer of target data for the I/O request between the host memory and the non-volatile memory module. A completion handling module writes a completion request in the host memory and handles an interrupt when the data transferring module completes to process the I/O request. A second doorbell region is exposed to the configuration space and updated when the I/O service is terminated by the host.

Abstract: A processor corresponding to a core of a coprocessor, a cache used as a buffer of the processor, and a flash controller are connected to an interconnect network. The flash controller and a flash memory are connected to a flash network. The flash controller reads or writes target data of a memory request from or to the flash memory.

Abstract: A method of supporting persistence of a computing device is provided. The computing device performs a stop procedure upon power failure. In the stop procedure, the computing device schedules out a running process task, stores a state of the process task to a process control block of a memory module including a non-volatile memory, flushes a cache for the processor, and flushes a pending memory request.

Abstract: Provided herein is a storage node of a distributed storage system and a method of operating the same. A memory controller may include a data controller configured to receive a write request and write data corresponding to the write request from a host, and configured to determine a physical address of a memory block in which the write data is to be stored based on chunk type information included in the write request, a memory control component configured to provide a program command for instructing the memory block to store the write data, the physical address, and the write data to the memory device, wherein the chunk type information is information about whether the write data indicates a type of data chunks or a type of coding chunks, the data chunks and the coding chunks being generated by the host performing an erasure coding operation on original data.

Abstract: An electronic device is provided. A memory controller, having an improved response time for an input/output request and capacity of Dynamic Random Access Memory (DRAM) according to the present disclosure, includes an available-time prediction component configured to perform a machine learning operation using a Recurrent Neural Network (RNN) model based on input/output request information about an input/output request input from a host, and to predict an idle time representing a time during which the input/output request is not expected to be input from the host and a data compression controller configured to generate, in response to the idle time longer than a set reference time, compressed map data by compressing map data which indicates a mapping relationship between a logical address provided by the host and a physical address indicating a physical location of a memory block included in the memory device.

Abstract: A method for operating a graph processing system including a first and second memory, comprising: storing in the first memory, a start index, a terminal index and an edge value of graph data; storing in the second memory, a start vertex of the graph data; rearranging the start vertex as an intermediate vertex by using to the start index; performing a graph computation on the intermediate vertex by using to the terminal index and the edge value; storing in the second memory, a terminal vertex as a result of the graph computation; determining whether a graph processing operation is completed by comparing the terminal vertex and the start vertex; setting the terminal vertex as the start vertex when the graph processing operation is not completed; and iterating the rearranging, the performing, the storing the terminal vertex, the determining and the setting until the graph processing operation is completed.

Abstract: In a coprocessor performing data processing by supplementing functions of a CPU of a host or independently of the CPU, a processing element corresponding to a core of the coprocessor executes a kernel transferred from the host, and a server manages a memory request generated according to an execution of the kernel by the processing element. A memory controller connected to the resistance switching memory module moves data corresponding to the memory request between the resistance switching memory module and the processing element in accordance with the memory request transferred from the server. A network integrates the processing element, the server, and the memory controller.

Abstract: A memory system including a memory subsystem and a memory controller is provided. The memory subsystem includes a plurality of first memory modules implemented by a phase-change memory and a second memory module implemented by a memory whose write speed is faster than that of the phase-change memory. The memory controller generates a non-blocking code from a plurality of sub-data into which original data are divided, writes the non-blocking code to the second memory module, writes the plurality of sub-data to the plurality of first memory modules, respectively, and reconstructs the original data from some sub-data of the plurality of sub-data which are read from some of the plurality of first memory modules and the non-blocking code read from the second memory under a predetermined condition at a read request.

Abstract: A memory controlling device of a computing device including a CPU, a memory, and a flash-based storage device is provided. The memory controlling device includes an address manager and an interface. The address manager aggregates a memory space of the memory and a storage space of the storage device into an expanded memory space, and handles a memory request for the expanded memory space from the CPU by using the memory space of the memory as a cache for the storage space of the storage device. The interface is used to access the memory and the storage device.

Abstract: A resistance switching memory-based accelerator configured to be connected to a host including a CPU and a system memory is provided. A resistance switching memory module includes a memory cell array including a plurality of resistance switching memory cells, and stores a kernel offloaded from the host. An accelerator core includes a plurality of processing elements, and the kernel is executed by a target processing element among the plurality of processing elements. An MCU manages a memory request generated in accordance with execution of the kernel by the target processing element. A memory controller is connected to the resistance switching memory module, and allows data according to the memory request to move between the resistance switching memory module and the target processing element, in accordance with the memory request transferred from the MCU. A network integrates the accelerator core, the plurality of processing elements, and the memory controller.

Abstract: A flash-based accelerator configured to be connected to a host including a CPU and a system memory is provided. A plurality of processors execute a plurality of kernels offloaded from the host. A memory system includes a first memory that is used to map a data section of each kernel to the flash memory. A supervisor processor maps a region of the first memory pointed by a data section of a first kernel to a region of the flash memory to allow first data to move between the region of the first memory and the region of the flash memory, based on a first message which is transferred in accordance with execution of the first kernel by a first processor among the plurality of processors. A network integrates the flash backbone, the memory system, the plurality of processors, and the supervisor processor.

Abstract: A magnetoresistive memory module used as a main memory of a computing device is provided. A plurality of memory chips are mounted on a printed circuit board, and a memory controller performs data scrubbing. Each memory chip includes a plurality of magnetoresistive memory cells. Each magnetoresistive memory cell includes a magnetoresistive element and an access transistor that transfers a current to the magnetoresistive element, and has a size of a cell area that is substantially similar to a size of a DRAM cell area.

Abstract: In a flash-based accelerator, a flash-based non-volatile memory stores data in pages, and a buffer subsystem stores data in words or bytes. An accelerator controller manages data movement between the flash-based non-volatile memory and the buffer subsystem. A plurality of processors processes data stored in the buffer subsystem. A network integrates the flash-based non-volatile memory, the buffer subsystem, the accelerator controller, and the plurality of processors.

Abstract: A memory controlling device configured to connect to a memory module including a resistance switching memory cell array which is partitioned into a plurality of partitions including a first partition and a second partition is provided. A first controlling module accesses the memory module. A second controlling module determines whether there is a conflict for the first partition to which a read request targets when an incoming request is the read request, instructs the first controlling module to read target data of the read request from the memory module when a write to the second partition is in progress, and suspends the read request when a write to the first partition is in progress.

Abstract: A memory controlling device configured to connect to a first memory module including a resistance switching memory cell array which is partitioned into a plurality of partitions and a second memory module used for a cache is provided. A cache controller splits an address of a read request into at least a first cache index and a first tag, and determines whether the read request is a cache hit or a cache miss by referring to a lookup logic based on the first cache index and the first tag. The cache controller instructs the memory controller to read target data of the read request from the first memory module when the read request targets to the second partition in a case where the read request is the cache miss and a write to the first partition is in progress.

Abstract: A memory system including a memory subsystem and a memory controller is provided. The memory subsystem includes a plurality of first memory modules implemented by a phase-change memory and a second memory module implemented by a memory whose write speed is faster than that of the phase-change memory. The memory controller generates a non-blocking code from a plurality of sub-data into which original data are divided, writes the non-blocking code to the second memory module, writes the plurality of sub-data to the plurality of first memory modules, respectively, and reconstructs the original data from some sub-data of the plurality of sub-data which are read from some of the plurality of first memory modules and the non-blocking code read from the second memory under a predetermined condition at a read request.

Abstract: A memory system including a memory subsystem and a memory controller is provided. The memory subsystem includes a plurality of first memory modules implemented by a phase-change memory and a second memory module implemented by a memory whose write speed is faster than that of the phase-change memory. The memory controller generates a non-blocking code from a plurality of sub-data into which original data are divided, writes the non-blocking code to the second memory module, writes the plurality of sub-data to the plurality of first memory modules, respectively, and reconstructs the original data from some sub-data of the plurality of sub-data which are read from some of the plurality of first memory modules and the non-blocking code read from the second memory under a predetermined condition at a read request.

Abstract: A memory controlling device configured to connect to a first memory module including a resistance switching memory cell array which is partitioned into a plurality of partitions and a second memory module used for a cache is provided. A cache controller splits an address of a read request into at least a first cache index and a first tag, and determines whether the read request is a cache hit or a cache miss by referring to a lookup logic based on the first cache index and the first tag. The cache controller instructs the memory controller to read target data of the read request from the first memory module when the read request targets to the second partition in a case where the read request is the cache miss and a write to the first partition is in progress.

Abstract: A magnetoresistive memory module used as a main memory of a computing device is provided. A plurality of memory chips are mounted on a printed circuit board, and a memory controller performs data scrubbing. Each memory chip includes a plurality of magnetoresistive memory cells. Each magnetoresistive memory cell includes a magnetoresistive element and an access transistor that transfers a current to the magnetoresistive element, and has a size of a cell area that is substantially similar to a size of a DRAM cell area.

Abstract: A memory controlling device of a computing device including a CPU, a memory, and a flash-based storage device is provided. The memory controlling device includes an address manager and an interface. The address manager aggregates a memory space of the memory and a storage space of the storage device into an expanded memory space, and handles a memory request for the expanded memory space from the CPU by using the memory space of the memory as a cache for the storage space of the storage device. The interface is used to access the memory and the storage device.