Abstract: A computing device includes a CPU, a CPU memory for CPU, a non-volatile memory, a coprocessor using the non-volatile memory, a coprocessor memory for storing data to be processed by the coprocessor or data processed by the coprocessor, and a recording medium. The recording medium includes a controller driver for the non-volatile memory and a library that are executed by the CPU. The controller driver maps the coprocessor memory to a system memory block of the CPU memory. The library moves data between the coprocessor and the non-volatile memory via the system memory block mapped to the coprocessor memory.

Abstract: A flash-based accelerator configured to be connected to a host including a CPU and a system memory is provided. A plurality of processors execute a plurality of kernels offloaded from the host. A memory system includes a first memory that is used to map a data section of each kernel to the flash memory. A supervisor processor maps a region of the first memory pointed by a data section of a first kernel to a region of the flash memory to allow first data to move between the region of the first memory and the region of the flash memory, based on a first message which is transferred in accordance with execution of the first kernel by a first processor among the plurality of processors. A network integrates the flash backbone, the memory system, the plurality of processors, and the supervisor processor.

Abstract: A resistance switching memory-based accelerator configured to be connected to a host including a CPU and a system memory is provided. A resistance switching memory module includes a memory cell array including a plurality of resistance switching memory cells, and stores a kernel offloaded from the host. An accelerator core includes a plurality of processing elements, and the kernel is executed by a target processing element among the plurality of processing elements. An MCU manages a memory request generated in accordance with execution of the kernel by the target processing element. A memory controller is connected to the resistance switching memory module, and allows data according to the memory request to move between the resistance switching memory module and the target processing element, in accordance with the memory request transferred from the MCU. A network integrates the accelerator core, the plurality of processing elements, and the memory controller.

Abstract: A computing device includes a CPU, a CPU memory for CPU, a non-volatile memory, a coprocessor using the non-volatile memory, a coprocessor memory for storing data to be processed by the coprocessor or data processed by the coprocessor, and a recording medium. The recording medium includes a controller driver for the non-volatile memory and a library that are executed by the CPU. The controller driver maps the coprocessor memory to a system memory block of the CPU memory. The library moves data between the coprocessor and the non-volatile memory via the system memory block mapped to the coprocessor memory.

Abstract: In a memory controller, a request handler processes a write request which is issued from a CPU and requests data write to a memory device using a phase change memory, and a request queue stores the write request. A scheduler returns a completion on the write request to the CPU when a predetermined write time has elapsed. The predetermined write time is shorter than a write latency time that is taken to complete the data write to a memory cell of the memory device in response to the write request.

Abstract: A computing device includes a CPU, a CPU memory for CPU, a non-volatile memory, a coprocessor using the non-volatile memory, a coprocessor memory for storing data to be processed by the coprocessor or data processed by the coprocessor, and a recording medium. The recording medium includes a controller driver for the non-volatile memory and a library that are executed by the CPU. The controller driver maps the coprocessor memory to a system memory block of the CPU memory. The library moves data between the coprocessor and the non-volatile memory via the system memory block mapped to the coprocessor memory.

Abstract: In a coprocessor performing data processing by supplementing functions of a CPU of a host or independently of the CPU, a processing element corresponding to a core of the coprocessor executes a kernel transferred from the host, and a server manages a memory request generated according to an execution of the kernel by the processing element. A memory controller connected to the resistance switching memory module moves data corresponding to the memory request between the resistance switching memory module and the processing element in accordance with the memory request transferred from the server. A network integrates the processing element, the server, and the memory controller.

Abstract: In a memory controller, a request handler processes a write request which is issued from a CPU and requests data write to a memory device using a phase change memory, and a request queue stores the write request. A scheduler returns a completion on the write request to the CPU when a predetermined write time has elapsed. The predetermined write time is shorter than a write latency time that is taken to complete the data write to a memory cell of the memory device in response to the write request.

Abstract: A memory controller of a memory device that uses a phase change memory and includes a memory cell array partitioned into a plurality of partitions is provided. A write request that request a data write to the memory device and a read request which request a data read from the memory device are inserted to a request queue. A scheduler, in a case that a conflict check condition including a first condition that a write operation is being performed in a first partition among the plurality of partitions is satisfied, creates a read command for a second partition based on a read request for the second partition when the request queue includes the read request for the second partition. The second partition is a partition, in which a read operation does not conflict with the write operation in the first partition, among the plurality of partitions.

Abstract: In a flash-based accelerator, a flash-based non-volatile memory stores data in pages, and a buffer subsystem stores data in words or bytes. An accelerator controller manages data movement between the flash-based non-volatile memory and the buffer subsystem. A plurality of processors processes data stored in the buffer subsystem. A network integrates the flash-based non-volatile memory, the buffer subsystem, the accelerator controller, and the plurality of processors.

Abstract: A computing device includes a CPU, a CPU memory for CPU, a non-volatile memory, a coprocessor using the non-volatile memory, a coprocessor memory for storing data to be processed by the coprocessor or data processed by the coprocessor, and a recording medium. The recording medium includes a controller driver for the non-volatile memory and a library that are executed by the CPU. The controller driver maps the coprocessor memory to a system memory block of the CPU memory. The library moves data between the coprocessor and the non-volatile memory via the system memory block mapped to the coprocessor memory.

Abstract: A memory system includes a memory device having a cache area and a main area, and a memory controller configured to control the memory device, wherein the memory controller is configured to dump file data into the cache area in response to a flush cache command.