Abstract: An integrated circuit includes a processing engine configured to execute instructions that are synchronized using a set of events. The integrated circuit also includes a set of event registers and an age bit register. Each event in the set of events corresponds to a respective event register in the set of event registers. The age bit register includes a set of age bits, where each age bit in the age bit register corresponds to a respective event register in the set of event registers. Each age bit in the age bit register is configured to be set by an external circuit and to be cleared in response to a value change in a corresponding event register in the set of event registers. Executing the instructions by the processing engine changes a value of an event register in the set of event registers.

Abstract: Techniques for emulating a configuration space may include emulating a set of configuration registers for a set of functions corresponding to a type of peripheral device. The set of functions can include a physical function and a virtual function associated with the physical function. A configuration access request can be processed by retrieving an emulated configuration register from the emulated configuration space, and logging incoming configuration access requests in a configuration transaction log to track configuration accesses.

Abstract: Apparatus, methods, and computer-readable storage media are disclosed for core-to-core communication between physical and/or virtual processor cores. In some examples of the disclosed technology, application cores write notification data (e.g., to doorbell or PCI configuration memory space accesses via a memory interface), without synchronizing with the other application cores or the service cores. In one examples of the disclosed technology, a message selection circuit is configured to, serialize data from the plurality of user cores by: receiving data from a user core, selecting one of the service cores to send the data based on a memory location addressed by the sending user core, and sending the received data to a respective message buffer dedicated to the selected service core.

Abstract: A peripheral device may implement storage virtualization for non-volatile storage devices connected to the peripheral device. A host system connected to the peripheral device may host one or multiple virtual machines. The peripheral device may implement different virtual interfaces for the virtual machines or the host system that present a storage partition at a non-volatile storage device to the virtual machine or host system for storage. Access requests from the virtual machines or host system are directed to the respective virtual interface at the peripheral device. The peripheral device may perform data encryption or decryption, or may perform throttling of access requests. The peripheral device may generate and send physical access requests to perform the access requests received via the virtual interfaces to the non-volatile storage devices. Completion of the access requests may be indicated to the virtual machines via the virtual interfaces.

Abstract: Provided are systems and methods for reliable, out-of-order transmission of packets. In some implementations, provided is an apparatus configured to communicate with a network and a host device. The apparatus may receive messages from the host device at a send queue, where each message includes destination information. The apparatus may further determine, using the destination information and an identify of the send queue, a transport context associated with a destination on the network. The apparatus may further, for each message and using the transport context, generate a packet including the message and transmit the packet over the network. The apparatus may further monitor status for each transmitted packet.

Abstract: Techniques for emulating a configuration space by a peripheral device may include receiving a access request, determining that the access request is for an emulated configuration space of the peripheral device, and retrieving an emulated configuration from an emulated configuration space. The access request can then be serviced by using the emulated configuration.

Abstract: An integrated circuit is configurable to generate a notification message when an indicator of an event used to synchronize the execution of different functional blocks of the integrated circuit changes status. The indicator of the event is cleared when an operation is triggered and is set when the operation completes. The notification message includes a timestamp indicating the time when the indicator of the event changes status. The notification message is used to determine the execution timeline of a set of instructions executed by integrated circuit and to identify bottlenecks in the set of instructions or the integrated circuit.

Abstract: Methods and apparatus are disclosed for securely erasing partitions of reconfigurable logic devices such as FPGAs in a multi-tenant server environment. In one example, a method of securely erasing an FPGA includes identifying one partition of previously-programmed resources in the FPGA, erasing the identified partition by storing new values in memory or storage elements of the identified partition, and storing new values in memory or storage elements of additional external resources electrically connected to the integrated circuit and associated with the identified partition. Thus, other partitions and subsequent users of the identified partition are prevented from accessing the securely erased data. A configuration circuit, accessible by a host computer via DMA, can be programmed into the FPGA reconfigurable logic for performing the disclosed erasing operations.

Abstract: A resource manager of a virtualized computing service indicates to a client that FPGA-enabled compute instances are supported at the service. From a set of virtualization hosts of the service, a particular host from which an FPGA is accessible is selected for the client based on an indication of computation objectives of the client. Configuration operations are performed to prepare the host for the application, and an FPGA-enabled compute instance is launched at the host for the client.

Abstract: The following description is directed to a logic repository service. In one example, a method of a logic repository service can include receiving a first request to generate configuration data for configurable hardware using a specification for application logic of the configurable hardware. The method can include generating the configuration data for the configurable hardware. The configuration data can include data for implementing the application logic. The method can include encrypting the configuration data to generate encrypted configuration data. The method can include signing the encrypted configuration data using a private key. The method can include transmitting the signed encrypted configuration data in response to the request.

Abstract: Provided are systems and methods for a storage adapter device for communicating with network storage. In some implementations, the storage adapter device comprises a host interface. In these implementations, the host interface may be configured to communicate with a host device using a local bus protocol. In some implementations, the storage adapter device also includes a network interface. In these implementations, the network interface may communicate with a network using a network protocol. In some implementations, the storage adapter device may be configured to communicate with a remote storage device. In some implementations, the storage adapter device may also be configured to translate a request from the host interface from the local bus protocol to the network protocol. The storage adapter device may further be configured to transmit the translated request to the remote storage device.

Abstract: A peripheral device may implement storage virtualization for non-volatile storage devices connected to the peripheral device. A host system connected to the peripheral device may host one or multiple virtual machines. The peripheral device may implement different virtual interfaces for the virtual machines or the host system that present a storage partition at a non-volatile storage device to the virtual machine or host system for storage. Access requests from the virtual machines or host system are directed to the respective virtual interface at the peripheral device. The peripheral device may perform data encryption or decryption, or may perform throttling of access requests. The peripheral device may generate and send physical access requests to perform the access requests received via the virtual interfaces to the non-volatile storage devices. Completion of the access requests may be indicated to the virtual machines via the virtual interfaces.

Abstract: A technique for remote direct memory access (RDMA) may include receiving a packet that was sent over a network, and determining the packet has metadata used for queue selection. The technique may also include selecting a queue based on the metadata, and writing the data of the packet to an application memory using the datapath associated with the selected queue. Amended metadata can be generated to indicate that the data has been written to the application memory, and the amended metadata can be stored in a software accessible buffer.

Abstract: Methods, systems, and computer-readable media for virtualizing graphics processing in a provider network are disclosed. A virtual compute instance is provisioned from a provider network. The provider network comprises a plurality of computing devices configured to implement a plurality of virtual compute instances with multi-tenancy. A virtual GPU is attached to the virtual compute instance. The virtual GPU is implemented using a physical GPU, and the physical GPU is accessible to the virtual compute instance over a network. An application is executed using the virtual GPU on the virtual compute instance. Executing the application generates virtual GPU output that is provided to a client device.

Abstract: Technologies are provided for dynamically changing a size of a cache region of a storage device. A storage device controller writes data to the cache region of the storage device using a particular storage format. The storage device controller then migrates the cached data to a storage region of the device, where the data is written using a different storage format. A dynamic cache manager monitors input and output activity for the storage device and dynamically adjusts a size of the cache region to adapt to changes in the input and/or output activity. The dynamic cache manager can also adjust a size of the storage region. The storage device controller can automatically detect that the storage device has dynamic cache support and configure the storage device by creating the cache region and the storage region on the device.

Abstract: Methods and apparatus are disclosed for programming reconfigurable logic devices such as FPGAs in a networked server environment. In one example, a system hosting a network service providing field programmable gate array (FPGA) services includes a network service provider configured to receive a request to implement application logic in a plurality of FPGAs, allocate a computing instance comprising the FPGAs in responses to receiving the request, produce configuration information for programming the FPGAs, and send the configuration information to an allocated computing instance. The system further includes a computing host that is allocated by the network service provider as a computing instance which includes memory, processors configured to execute computer-executable instructions stored in the memory, and the programmed FPGAs.

Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a plurality of reconfigurable logic regions. Each reconfigurable region can include hardware that is configurable to implement an application logic design. The host logic can be used for separately encapsulating each of the reconfigurable logic regions. The host logic can include a plurality of data path functions where each data path function can include a layer for formatting data transfers between a host interface and the application logic of a corresponding reconfigurable logic region. The host interface can be configured to apportion bandwidth of the data transfers generated by the application logic of the respective reconfigurable logic regions.

Abstract: The following description is directed to a logic repository service. In one example, a method of a logic repository service can include receiving a first request to generate configuration data for configurable hardware using a specification for application logic of the configurable hardware. The method can include generating the configuration data for the configurable hardware. The configuration data can include data for implementing the application logic. The method can include encrypting the configuration data to generate encrypted configuration data. The method can include signing the encrypted configuration data using a private key. The method can include transmitting the signed encrypted configuration data in response to the request.

Abstract: A technique for remote direct memory access (RDMA) may include receiving a packet that was sent over a network, and determining the packet has metadata indicative of acceleration. The technique may also include selecting a queue having minimal storage stages to process the packet, and writing the data of the packet to an application memory using the datapath associated with the queue. Amended metadata can be generated to indicate that the data has been written to the application memory, and the amended metadata can be stored in a software accessible buffer.

Abstract: A method for in-band de-duplication, the method may include receiving by a hardware accelerator, a received packet of a first sequence of packets that conveys a first data chunk; applying a data chunk hash calculation process on the received packet while taking into account a hash calculation result obtained when applying the data chunk hash calculation process on a last packet of the first sequence that preceded the received packet; wherein the calculating of the first data chunk hash value is initiated before a completion of a reception of the entire first data chunk by the hardware accelerator.