Patents by Inventor Nan-Chun Lien
Nan-Chun Lien has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11935581Abstract: A circuit module with reliable margin configuration, may include a main circuit, a first auxiliary circuit and a second auxiliary circuit. When the first auxiliary circuit is on, the second auxiliary circuit may be on or off according to whether a control signal is of a first level or a second level. When the first auxiliary circuit and the second auxiliary circuit are both on, the first auxiliary circuit and the second auxiliary circuit may jointly cause an operation parameter of the main circuit to be a first value. When the first auxiliary circuit is on and the second auxiliary circuit is off, the first auxiliary circuit may cause the operation parameter to be a second value. An operation margin of the main circuit may cover a range between the first value and the second value.Type: GrantFiled: May 31, 2022Date of Patent: March 19, 2024Assignee: M31 TECHNOLOGY CORPORATIONInventors: Li-Wei Chu, Nan-Chun Lien
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Publication number: 20230352060Abstract: A circuit module with improved line load, may comprise a first line, a first switch, a second line, a second switch and a second driver. The first switch may be on and off to conduct and stop conducting between the first line and a first node. The second switch may be on and off to conduct and stop conducting between the second line and the first node. The second driver, coupled to the second line, may be enabled to drive the second line according to a voltage of a second node, and may be disabled to stop driving the second line. The voltage of the second node may be controlled by a voltage of the first node. When the first switch is on, the second switch may be off. When the second switch is off, the second driver may be enabled.Type: ApplicationFiled: July 12, 2023Publication date: November 2, 2023Inventors: Nan-Chun LIEN, Li-Wei CHU, Ting-Wei CHANG
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Publication number: 20230335188Abstract: A memory module with improved timing adaptivity of sensing amplification, comprises at least one sensing amplifier, a tracking word line, a tracking bit line and a pulse-width controller. The tracking word line comprises a front node and an end node. Each said sensing amplifier is enabled/disabled when an enabling signal is activated/deactivated. The pulse-width controller is coupled to the tracking bit line, the front node and the end node. When a voltage of the tracking bit line changes to a predetermined voltage, the pulse-width controller activates the enabling signal, and causes a voltage of the front node to change. When the voltage of the front node changes, the tracking word line causes a voltage of the end node to change after a first delay time. When the voltage of the end node changes, the pulse-width controller deactivates the enabling signal after a second delay time.Type: ApplicationFiled: March 31, 2023Publication date: October 19, 2023Inventors: Po-Yu WU, Hao-I YANG, Nan-Chun LIEN
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Patent number: 11742000Abstract: A circuit module with improved line load, may comprise a first line, a first switch, a second line, a second switch and a second driver. The first switch may be on and off to conduct and stop conducting between the first line and a first node. The second switch may be on and off to conduct and stop conducting between the second line and the first node. The second driver, coupled to the second line, may be enabled to drive the second line according to a voltage of a second node, and may be disabled to stop driving the second line. The voltage of the second node may be controlled by a voltage of the first node. When the first switch is on, the second switch may be off. When the second switch is off, the second driver may be enabled.Type: GrantFiled: November 9, 2021Date of Patent: August 29, 2023Assignee: M31 TECHNOLOGY CORPORATIONInventors: Nan-Chun Lien, Li-Wei Chu, Ting-Wei Chang
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Publication number: 20230040348Abstract: A circuit module with improved line load, may comprise a first line, a first switch, a second line, a second switch and a second driver. The first switch may be on and off to conduct and stop conducting between the first line and a first node. The second switch may be on and off to conduct and stop conducting between the second line and the first node. The second driver, coupled to the second line, may be enabled to drive the second line according to a voltage of a second node, and may be disabled to stop driving the second line. The voltage of the second node may be controlled by a voltage of the first node. When the first switch is on, the second switch may be off. When the second switch is off, the second driver may be enabled.Type: ApplicationFiled: November 9, 2021Publication date: February 9, 2023Inventors: Nan-Chun LIEN, Li-Wei CHU, Ting-Wei CHANG
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Publication number: 20220399052Abstract: A circuit module with reliable margin configuration, may include a main circuit, a first auxiliary circuit and a second auxiliary circuit. When the first auxiliary circuit is on, the second auxiliary circuit may be on or off according to whether a control signal is of a first level or a second level. When the first auxiliary circuit and the second auxiliary circuit are both on, the first auxiliary circuit and the second auxiliary circuit may jointly cause an operation parameter of the main circuit to be a first value. When the first auxiliary circuit is on and the second auxiliary circuit is off, the first auxiliary circuit may cause the operation parameter to be a second value. An operation margin of the main circuit may cover a range between the first value and the second value.Type: ApplicationFiled: May 31, 2022Publication date: December 15, 2022Inventors: Li-Wei CHU, Nan-Chun LIEN
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Patent number: 10074418Abstract: A SRAM module and a writing control method of the SRAM module are disclosed. The writing control method of the SRAM module is applied to a SRAM module that includes a plurality of memory cells and a bit line. The method includes: providing a first voltage as a supply voltage of the plurality of memory cells during a data retention time; decreasing a first voltage level corresponding to the data retention time of the memory cells to a second voltage level by discharging the memory cells; and performing a write process to the memory cells through the bit line. The discharge time from the first voltage level to the second voltage level is related to the number of the memory cells.Type: GrantFiled: December 11, 2017Date of Patent: September 11, 2018Assignee: M31 Technology CorporationInventors: Nan-Chun Lien, David C. Yu
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Patent number: 10014035Abstract: A control device includes: a dummy memory cell group; a transistor having a first terminal, a grounded second terminal and a control terminal; an adjustor providing a resistance between the dummy memory cell group and the first terminal of the transistor; an inverter generating, based on a voltage at the first terminal of the transistor, a sense start signal that is associated with switching of a sense amplifier circuit of a semiconductor memory device from a disabled state to an enabled state; and a controller generating, based on the sense start signal, a control signal for controlling the transistor such that switching of the transistor from conduction into non-conduction is associated with the sense start signal.Type: GrantFiled: August 10, 2017Date of Patent: July 3, 2018Assignee: M31 TECHNOLOGY CORPORATIONInventors: Yu-Fen Lin, Nan-Chun Lien
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Publication number: 20180102165Abstract: A SRAM module and a writing control method of the SRAM module are disclosed. The writing control method of the SRAM module is applied to a SRAM module that includes a plurality of memory cells and a bit line. The method includes: providing a first voltage as a supply voltage of the plurality of memory cells during a data retention time; decreasing a first voltage level corresponding to the data retention time of the memory cells to a second voltage level by discharging the memory cells; and performing a write process to the memory cells through the bit line. The discharge time from the first voltage level to the second voltage level is related to the number of the memory cells.Type: ApplicationFiled: December 11, 2017Publication date: April 12, 2018Inventors: NAN-CHUN LIEN, DAVID C. YU
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Publication number: 20180047431Abstract: A control device includes: a dummy memory cell group; a transistor having a first terminal, a grounded second terminal and a control terminal; an adjustor providing a resistance between the dummy memory cell group and the first terminal of the transistor; an inverter generating, based on a voltage at the first terminal of the transistor, a sense start signal that is associated with switching of a sense amplifier circuit of a semiconductor memory device from a disabled state to an enabled state; and a controller generating, based on the sense start signal, a control signal for controlling the transistor such that switching of the transistor from conduction into non-conduction is associated with the sense start signal.Type: ApplicationFiled: August 10, 2017Publication date: February 15, 2018Inventors: Yu-Fen LIN, Nan-Chun LIEN
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Patent number: 9870817Abstract: A SRAM module and a writing control method of the SRAM module are disclosed. The writing control method of the SRAM module is applied to a SRAM module that includes a plurality of memory cells and a bit line. The method includes: providing a first voltage as a supply voltage of the plurality of memory cells during a data retention time; decreasing a first voltage level corresponding to the data retention time of the memory cells to a second voltage level by discharging the memory cells; and performing a write process to the memory cells through the bit line. The discharge time from the first voltage level to the second voltage level is related to the number of the memory cells.Type: GrantFiled: June 3, 2015Date of Patent: January 16, 2018Assignee: M31 Technology CorporationInventors: Nan-Chun Lien, David C. Yu
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Patent number: 9728250Abstract: A memory write tracking device is applied to a data write operation to at least a memory cell row. The memory write tracking device includes a dummy cell row, a variation sensor, a judging device and a word-line pulse generator. The dummy cell row includes a plurality of dummy memory cells for simulating the data write operation to the memory cell row. The variation sensor senses a set of circuit parameters for write ability of the memory cell row. The judging device determines a threshold number according to a change of the set of circuit parameters and sends an enabling signal when a threshold number of the dummy memory cells have been successfully written with the data. The word-line pulse generator determines a write cycle of the data write operation in response to the enabling signal. An associated memory write tracking method is also provided.Type: GrantFiled: October 17, 2016Date of Patent: August 8, 2017Assignee: M31 Technology CorporationInventors: Chao-Kuei Chung, Nan-Chun Lien
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Publication number: 20170110183Abstract: A memory write tracking device is applied to a data write operation to at least a memory cell row. The memory write tracking device includes a dummy cell row, a variation sensor, a judging device and a word-line pulse generator. The dummy cell row includes a plurality of dummy memory cells for simulating the data write operation to the memory cell row. The variation sensor senses a set of circuit parameters for write ability of the memory cell row. The judging device determines a threshold number according to a change of the set of circuit parameters and sends an enabling signal when a threshold number of the dummy memory cells have been successfully written with the data. The word-line pulse generator determines a write cycle of the data write operation in response to the enabling signal. An associated memory write tracking method is also provided.Type: ApplicationFiled: October 17, 2016Publication date: April 20, 2017Inventors: Chao-Kuei CHUNG, Nan-Chun LIEN
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Patent number: 9496014Abstract: The present invention discloses a random access memory and the memory access method thereof capable of avoiding read disturbance and increasing reading speed. An embodiment of the said random access memory comprises: a word line; a word line driving unit, coupled to the word line, operable to receive an access control signal to generate a word line enablement voltage; a voltage adjusting unit including a switch and a capacitor in which the switch is coupled to the word line and operable to receive a control signal to determine a conduction state of the switch itself and the capacitor is coupled to the switch and operable to adjust a voltage level of the word line enablement voltage according to the conduction state; and a memory unit, coupled to the word line, operable to be enabled according to the word line enablement voltage.Type: GrantFiled: May 26, 2015Date of Patent: November 15, 2016Assignee: M31 Technology CorporationInventors: David C. Yu, Nan-Chun Lien
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Publication number: 20160232955Abstract: The present invention discloses a random access memory and the memory access method thereof capable of avoiding read disturbance and increasing reading speed. An embodiment of the said random access memory comprises: a word line; a word line driving unit, coupled to the word line, operable to receive an access control signal to generate a word line enablement voltage; a voltage adjusting unit including a switch and a capacitor in which the switch is coupled to the word line and operable to receive a control signal to determine a conduction state of the switch itself and the capacitor is coupled to the switch and operable to adjust a voltage level of the word line enablement voltage according to the conduction state; and a memory unit, coupled to the word line, operable to be enabled according to the word line enablement voltage.Type: ApplicationFiled: May 26, 2015Publication date: August 11, 2016Inventors: DAVID C. YU, NAN-CHUN LIEN
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Publication number: 20160232965Abstract: A SRAM module and a writing control method of the SRAM module are disclosed. The writing control method of the SRAM module is applied to a SRAM module that includes a plurality of memory cells and a bit line. The method includes: providing a first voltage as a supply voltage of the plurality of memory cells during a data retention time; decreasing a first voltage level corresponding to the data retention time of the memory cells to a second voltage level by discharging the memory cells; and performing a write process to the memory cells through the bit line. The discharge time from the first voltage level to the second voltage level is related to the number of the memory cells.Type: ApplicationFiled: June 3, 2015Publication date: August 11, 2016Inventors: NAN-CHUN LIEN, DAVID C. YU
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Patent number: 9378808Abstract: A pulse width modulation device for use in an N-ports random access memory having a plurality of word line sets, wherein a specified word line set comprises N port word lines. The pulse width modulation device comprises a status detecting device and a clock signal generator. The status detecting device is coupled to the N port word lines having a first and a second port word line, and outputs a first control signal when both the voltage values of the first and second port word lines are within a first level range. The clock signal generator is coupled to the status detecting device and the specified word line set, and generates and outputs a first clock signal to the specified word line set, wherein a duration of the first clock signal kept within the first level range is variable in response to the first control signal.Type: GrantFiled: January 23, 2015Date of Patent: June 28, 2016Assignee: M31 Technology CorporationInventors: Nan-Chun Lien, Chen-Wei Lin, Chao-Kuei Chung, Li-Wei Chu, Yuh-Jiun Lin, Yu-Wei Yeh, Wei-Chiang Shih
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Patent number: 9336865Abstract: A multi-port SRAM module includes a cell array comprising a plurality of cells, each having a first port and a second port; a first word line which is coupled to a plurality of cells of a target row to open and close the first port; a second word line which is coupled to the cells of the target row to open and close the second port; and a switch, which is coupled to the first word line and the second word line and couples the second word line to a reference voltage level according to a voltage level of the first word line.Type: GrantFiled: August 17, 2015Date of Patent: May 10, 2016Assignee: M31 TECHNOLOGY CORPORATIONInventors: Li-Wei Chu, Nan-Chun Lien
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Publication number: 20160111144Abstract: A pulse width modulation device for use in an N-ports random access memory having a plurality of word line sets, wherein a specified word line set comprises N port word lines. The pulse width modulation device comprises a status detecting device and a clock signal generator. The status detecting device is coupled to the N port word lines having a first and a second port word line, and outputs a first control signal when both the voltage values of the first and second port word lines are within a first level range. The clock signal generator is coupled to the status detecting device and the specified word line set, and generates and outputs a first clock signal to the specified word line set, wherein a duration of the first clock signal kept within the first level range is variable in response to the first control signal.Type: ApplicationFiled: January 23, 2015Publication date: April 21, 2016Inventors: Nan-Chun LIEN, Chen-Wei Lin, Chao-Kuei CHUNG, Li-Wei CHU, Yuh-Jiun LIN, Yu-Wei YEH, Wei-Chiang SHIH
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Publication number: 20160104523Abstract: A static random access memory (SRAM) includes a voltage generator coupled to receive a positive power supply voltage, and to controllably generate a first power supply voltage, which is with a reduced level and is higher than a retention voltage during a specific period. A first inverter and a second inverter each is connected between the first power supply voltage and a second power supply voltage. The first inverter and the second inverter are cross-coupled, and the output nodes of the first inverter and the second inverter act as a bit node pair.Type: ApplicationFiled: October 8, 2014Publication date: April 14, 2016Inventor: Nan-Chun Lien