Patents by Inventor Nan-Chun Lien
Nan-Chun Lien has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160104523Abstract: A static random access memory (SRAM) includes a voltage generator coupled to receive a positive power supply voltage, and to controllably generate a first power supply voltage, which is with a reduced level and is higher than a retention voltage during a specific period. A first inverter and a second inverter each is connected between the first power supply voltage and a second power supply voltage. The first inverter and the second inverter are cross-coupled, and the output nodes of the first inverter and the second inverter act as a bit node pair.Type: ApplicationFiled: October 8, 2014Publication date: April 14, 2016Inventor: Nan-Chun Lien
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Patent number: 9299421Abstract: A static random access memory (SRAM) includes a voltage generator coupled to receive a positive power supply voltage, and to controllably generate a first power supply voltage, which is with a reduced level and is higher than a retention voltage during a specific period. A first inverter and a second inverter each is connected between the first power supply voltage and a second power supply voltage. The first inverter and the second inverter are cross-coupled, and the output nodes of the first inverter and the second inverter act as a bit node pair.Type: GrantFiled: October 8, 2014Date of Patent: March 29, 2016Assignee: M31 Technology CorporationInventor: Nan-Chun Lien
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Patent number: 9213789Abstract: A method of generating optimized memory instances using a memory compiler is disclosed. Data pertinent to describing a memory to be designed are provided, and front-end models and back-end models are made to supply a library. Design criteria are received via a user interface. Design of the memory is optimized among speed, power and area according to the provided library and the received design criteria, thereby generating memory instances.Type: GrantFiled: December 13, 2012Date of Patent: December 15, 2015Assignee: M31 TECHNOLOGY CORPORATIONInventors: Nan-Chun Lien, Hsiao-Ping Lin, Wei-Chiang Shih, Yu-Chun Lin, Yu-Wei Yeh
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Patent number: 9159403Abstract: A control circuit of SRAM and an operating method thereof are provided. The control circuit includes a memory array, a word-line driver, a boost circuit and a voltage level detecting circuit. The memory array includes a plurality of memory cells. Each memory cell includes a plurality of transistors. The word-line driver is to activate the word-line of the memory array for cell storage data access. The boost circuit is to provide the higher voltage source for the word-line driver and a first operating voltage for boosting the first operating voltage to a second operating voltage. The voltage level detecting circuit is detecting if the first operation voltage needs to be boosted with boost-operation and a detecting-trigger signal and controls the operating of the boost circuit based on the detecting-trigger signal, the first operating voltage and a predetermined voltage.Type: GrantFiled: January 10, 2013Date of Patent: October 13, 2015Assignee: National Chiao Tung UniversityInventors: Ching-Te Chuang, Nan-Chun Lien, Wei-Nan Liao, Li-Wei Chu, Chi-Shin Chang, Ming-Hsien Tu
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Patent number: 8854897Abstract: A static random access memory apparatus and a bit-line voltage controller includes a controller, a pull-up circuit, a pull-down circuit and a voltage keeping circuit. The controller receives a bank selecting signal and a clock signal, and decides a pull-up time period, a pull-down time period and a voltage keeping time period according to the bank selecting signal and the clock signal. The pull-up circuit pulls up a bit-line power according to a first reference voltage within the pull-up time period. The pull-down circuit pulls down the bit-line power according to a second reference voltage within the pull-down time period. The voltage keeping circuit keeps the bit-line power to equal to an output voltage during the voltage keeping time period. The voltage keeping time period is after the pull-up time period and the pull-down time period.Type: GrantFiled: November 1, 2012Date of Patent: October 7, 2014Assignees: Faraday Technology Corp., National Chiao Tung UniversityInventors: Ching-Te Chuang, Nan-Chun Lien, Wei-Nan Liao, Chi-Hsin Chang, Hao-I Yang, Wei Hwang, Ming-Hsien Tu
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Patent number: 8804445Abstract: The present invention provides an oscillator which is based on a 6T SRAM for measuring the Bias Temperature Instability. The oscillator includes a first control unit, a first inverter, a second control unit, and a second inverter. The first control unit is coupled with the first inverter. The second control unit is coupled with the second inverter. The first control unit and the second control unit is used to control the first inverter and the second inverter being selected, biased, and connected respectively, so that the NBTI and the PBTI of the SRAM can be measured separately, and the real time stability of the SRAM can be monitored immediately.Type: GrantFiled: May 31, 2012Date of Patent: August 12, 2014Assignee: National Chiao Tung UniversityInventors: Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang, Ming-Chien Tsai, Yi-Wei Lin, Hao-I Yang, Ming-Hsien Tu, Wei-Chiang Shih, Nan-Chun Lien, Kuen-Di Lee
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Publication number: 20140173241Abstract: A method of generating optimized memory instances using a memory compiler is disclosed. Data pertinent to describing a memory to be designed are provided, and front-end models and back-end models are made to supply a library. Design criteria are received via a user interface. Design of the memory is optimized among speed, power and area according to the provided library and the received design criteria, thereby generating memory instances.Type: ApplicationFiled: December 13, 2012Publication date: June 19, 2014Applicant: M31 TECHNOLOGY CORPORATIONInventors: Nan-Chun Lien, Hsiao-Ping Lin, Wei-Chiang Shih, Yu-Chun Lin, Yu-Wei Yeh
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Publication number: 20140063918Abstract: A control circuit of SRAM and an operating method thereof are provided. The control circuit includes a memory array, a word-line driver, a boost circuit and a voltage level detecting circuit. The memory array includes a plurality of memory cells. Each memory cell includes a plurality of transistors. The word-line driver is to activate the word-line of the memory array for cell storage data access. The boost circuit is to provide the higher voltage source for the word-line driver and a first operating voltage for boosting the first operating voltage to a second operating voltage. The voltage level detecting circuit is detecting if the first operation voltage needed boosted with boost-operation and a detecting-trigger signal and controls the operating of the boost circuit based on the detecting-trigger signal, the first operating voltage and a predetermined voltage.Type: ApplicationFiled: January 10, 2013Publication date: March 6, 2014Applicant: NATIONAL CHIAO TUNG UNIVERSITYInventors: Ching-Te CHUANG, Nan-Chun LIEN, Wei-Nan LIAO, Li-Wei CHU, Chi-Shin CHANG, Ming-Hsien TU
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Publication number: 20140009999Abstract: A static random access memory apparatus and a bit-line voltage controller thereof are disclosed. The bit-line voltage controller includes a controller, a pull-up circuit, a pull-down circuit and a voltage keeping circuit. The controller receives a bank selecting signal and a clock signal, and decides a pull-up time period, a pull-down time period and a voltage keeping time period according to the bank selecting signal and the clock signal. The pull-up circuit pulls up a bit-line power according to a first reference voltage within the pull-up time period. The pull-down circuit pulls down the bit-line power according to a second reference voltage within the pull-down time period. The voltage keeping circuit keeps the bit-line power to equal to an output voltage during the voltage keeping time period. The voltage keeping time period is after the pull-up time period and the pull-down time period.Type: ApplicationFiled: November 1, 2012Publication date: January 9, 2014Inventors: Ching-Te Chuang, Nan-Chun Lien, Wei-Nan Liao, Chi-Hsin Chang, Hao-I Yang, Wei Hwang, Ming-Hsien Tu
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Publication number: 20130301343Abstract: A threshold voltage measurement device is disclosed. The device is coupled to a 6T SRAM. The SRAM comprises two inverters each coupled to a FET. Power terminals of one inverter are in a floating state; the drain and source of the FET coupled to the inverter are short-circuited. Two voltage selectors, a resistor, an amplifier and the SRAM are connected in a negative feedback way. Different bias voltages are applied to the SRAM for measuring threshold voltages of two FETs of the other inverter and the FET coupled to the other inverter. The present invention uses a single circuit to measure the threshold voltages of the three FETs without changing the physical structure of the SRAM. Thereby is accelerated the measurement and decreased the cost of the fabrication process and measurement instruments.Type: ApplicationFiled: August 29, 2012Publication date: November 14, 2013Inventors: Ching-Te Chuang, Shyh-Jye Jou, Geng-Cing Lin, Shao-Cheng Wang, Yi-Wei Lin, Ming-Chien Tsai, Wei-Chiang Shih, Nan-Chun Lien, Kuen-Di Lee, Jyun-Kai Chu
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Patent number: 8582378Abstract: A threshold voltage measurement device is disclosed. The device is coupled to a 6T SRAM. The SRAM comprises two inverters each coupled to a FET. Power terminals of one inverter are in a floating state; the drain and source of the FET coupled to the inverter are short-circuited. Two voltage selectors, a resistor, an amplifier and the SRAM are connected in a negative feedback way. Different bias voltages are applied to the SRAM for measuring threshold voltages of two FETs of the other inverter and the FET coupled to the other inverter. The present invention uses a single circuit to measure the threshold voltages of the three FETs without changing the physical structure of the SRAM. Thereby is accelerated the measurement and decreased the cost of the fabrication process and measurement instruments.Type: GrantFiled: August 29, 2012Date of Patent: November 12, 2013Assignee: National Chiao Tung UniversityInventors: Ching-Te Chuang, Shyh-Jye Jou, Geng-Cing Lin, Shao-Cheng Wang, Yi-Wei Lin, Ming-Chien Tsai, Wei-Chiang Shih, Nan-Chun Lien, Kuen-Di Lee, Jyun-Kai Chu
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Publication number: 20130222071Abstract: The present invention provides an oscillator which is based on a 6T SRAM for measuring the Bias Temperature Instability. The oscillator includes a first control unit, a first inverter, a second control unit, and a second inverter. The first control unit is coupled with the first inverter. The second control unit is coupled with the second inverter. The first control unit and the second control unit is used to control the first inverter and the second inverter being selected, biased, and connected respectively, so that the NBTI and the PBTI of the SRAM can be measured separately, and the real time stability of the SRAM can be monitored immediately.Type: ApplicationFiled: May 31, 2012Publication date: August 29, 2013Applicant: National Chiao Tung UniversityInventors: Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang, Ming-Chien Tsai, Yi-Wei Lin, Hao-I Yang, Ming-Hsien Tu, Wei-Chiang Shih, Nan-Chun Lien, Kuen-Di Lee
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Publication number: 20130223136Abstract: The present invention provides a 6T SRAM including a first inverter, a second inverter, a first pass-gate transistor, and a second pass-gate transistor. The first inverter zs a first pull-up transistor and a first pull-down transistor. The second inverter includes a second pull-up transistor and a second pull-down transistor. The gate of the second pull-up transistor is coupled with the gate of the second pull-down transistor, and the drain of the second pull-up transistor is coupled with the drain of the second pull-down transistor. The SRAM can measure the trip voltage, the read disturb voltage, and the write margin by controlling the first bit line, the second bit line, the GND, the first word line, and the voltage source without changing of the physic parameter of the SRAM.Type: ApplicationFiled: May 31, 2012Publication date: August 29, 2013Applicant: National Chiao Tung UniversityInventors: Ching-Te CHUANG, Shyh-Jye Jou, Wei Hwang, Yi-Wei Lin, Ming-Chien Tsai, Hao-I Yang, Ming-Hsien Tu, Wei-Chiang Shih, Nan-Chun Lien, Kuen-Di Lee
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Patent number: 7868668Abstract: A power-on detector and a method thereof are provided. The power-on detector includes four transistors, two resistors, and a comparator. The power-on detector can detect an input voltage and then determine whether the power is turned on or not. The power-on determination is substantially immune to temperature variation. The power-on detector is noise-free and stable in various temperatures.Type: GrantFiled: May 13, 2009Date of Patent: January 11, 2011Assignee: Faraday Technology Corp.Inventors: Yung-Shin Kao, Nan-Chun Lien
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Publication number: 20100289529Abstract: A power-on detector and a method thereof are provided. The power-on detector includes four transistors, two resistors, and a comparator. The power-on detector can detect an input voltage and then determine whether the power is turned on or not. The power-on determination is substantially immune to temperature variation. The power-on detector is noise-free and stable in various temperatures.Type: ApplicationFiled: May 13, 2009Publication date: November 18, 2010Applicant: FARADAY TECHNOLOGY CORP.Inventors: Yung-Shin Kao, Nan-Chun Lien