Abstract: A character segmentation method and apparatus, and a computer-readable storage medium. The character segmentation method comprises: converting a character area image into a grayscale image (step 101); converting the grayscale image into an edge binary image by using an edge detection algorithm (step 102); acquiring character box segmentation blocks from the edge binary image by using a projection method (step 103); and determining a target character area from the character box segmentation blocks by using a contour detection algorithm, and performing character segmentation on the character area image according to the target character area (step 104).

Abstract: Methods and devices for generating a training sample, training a model and recognizing a character are provided. The method for generating a training sample comprises: acquiring an image of characters, and determining respective characters contained in the image; and using a projection method to determine weights of the respective characters contained in the image, tagging the image with labels according to the weights of the respective characters contained in the image, and forming a training sample. The method for training a model comprises: using the training sample to train a character recognition model. The method for recognizing a character comprises: using the character recognition model to perform character recognition. The above methods and devices realize accurate recognition of characters, such as double-half characters, contained in an image of a wheel-type meter, and can provide a highly accurate biased recognition result.

Abstract: A quantization method and device for a neural network model, and a computer-readable storage medium are provided. The method includes determining, from a neural network model, a target convolution kernel having an abnormal coefficient distribution, splitting the target convolution kernel so as to obtain a plurality of sub-convolution kernels, quantizing the plurality of sub-convolution kernels respectively to obtain a plurality of quantized convolution kernels, and replacing the target convolution kernel with the plurality of quantized convolution kernels. The method can reduce quantization errors.

Abstract: The invention provides a chip frequency modulation method and apparatus of a computing device, a hash board, a computing device and a storage medium. The chip frequency modulation method comprises: setting a plurality of working frequencies for the operational chip and causing the plurality of cores work at the respective working frequencies; analyzing a computing performance indicator of each core at its current working frequency; and modulating the current working frequency of the core up or down according to the computing performance indicator of the core modulating the frequency of a core with high computing performance up and modulating the frequency of a core with low computing performance down. Therefore, the invention can automatically modulate a frequency corresponding to each core according to the actual computing performance of each core in the operational chip of the computing device, thereby maximizing the computing performance of the cores.

Abstract: A computational heat dissipation structure includes a circuit board including a plurality of heating components; and a radiator provided corresponding to the circuit board; wherein a space between the adjacent heating components is negatively correlated with heat dissipation efficiency of a region where the adjacent heating components are located. Since the space between the adjacent heating components of the disclosure is negatively correlated with the heat dissipation efficiency of the region where the adjacent heating components are located, i.e., the higher the heat dissipation efficiency of the region where the adjacent heating components are located is, the smaller the space between the adjacent heating components in the region will be, the heat dissipation efficiencies corresponding to the heating components are balanced, and load of a fan is reduced.

Abstract: The invention provides a voltage-following series power supply circuit, comprising a power supply end and a ground end; a power supply module comprising an input end connected to the power supply end, and an output end for providing a power supply to two or more to-be-powered chips, the power supply module and the to-be-powered chips connected in series between the power supply end and the ground end; and at least one auxiliary power supply module for supplying an auxiliary power supply to the to-be-powered chips, wherein a voltage following module is further connected between the power supply end and the auxiliary power supply module for adjusting a voltage of the auxiliary power supply.

Abstract: A leakage compensation dynamic register, a data operation unit, a chip, a hash board, and a computing apparatus. The leakage compensation dynamic register comprises: an input terminal, an output terminal, a clock signal terminal, and an analog switch unit; a data latch unit for latching the data under control of the clock signal; and an output drive unit for inverting and outputting the data received from the data latch unit, the analog switch unit, the data latch unit, and the output drive unit being sequentially connected in series between the input terminal and the output terminal, and the analog switch unit and the data latch unit having a node therebetween, wherein the leakage compensation dynamic register further comprises a leakage compensation unit electrically connected between the node and the output terminal.

Abstract: A clock generation circuit, a latch using same, and a computing device are provided. The clock generation circuit includes an input end, configured to input a pulse signal; a first output end, configured to output a first clock signal; a second output end, configured to output a second clock signal; and an input drive circuit, a latch circuit, an edge shaping circuit, a feedback delay circuit, and an output drive circuit, where the input drive circuit, the latch circuit, the edge shaping circuit, the feedback delay circuit, and the output drive circuit are sequentially connected between the input end and the first output end as well as the second output end in series. A clock pulse can be effectively shaped, the use of a clock buffer can be reduced, and the correctness and accuracy of data transmission and latching can be improved.

Abstract: A data compression method, comprising: obtaining a plurality of values of a parameter and an occurrence probability of each of the plurality of values (S101), comparing the occurrence probability with a predetermined threshold, wherein values with the occurrence probability less than the predetermined threshold are first set of values, and values with the occurrence probability greater than or equal to the predetermined threshold are second set of values (S102); performing pretreatment on the first set of values (S103); and encoding the second set of values and the pretreated first set of values (S104). By means of the data compression method, the maximum codeword length can be effectively reduced, so as to reduce the requirements of a code table to the storage space.

Abstract: The invention provides an on-chip passive power supply compensation circuit, and an operational unit, a chip, a hash board and a computing device using the same. The on-chip passive power supply compensation circuit comprises: two or more to-be-powered voltage domains, wherein the to-be-powered voltage domains are connected in series between a power supply and ground; and two or more isolation regions, wherein the to-be-powered voltage domains are formed in the isolation regions, and the isolation regions are configured for isolating the to-be-powered voltage domains; the isolation regions are connected in series between the power supply and the ground, wherein the on-chip passive power supply compensation circuit further comprises power supply compensation units connected between the to-be-powered voltage domains and the isolation regions for providing power supply compensation to the to-be-powered voltage domains.

Abstract: A computational heat dissipation structure includes a circuit board including a plurality of heating components; and a radiator provided corresponding to the circuit board; wherein a space between the adjacent heating components is negatively correlated with heat dissipation efficiency of a region where the adjacent heating components are located. The computing device of the disclosure includes a device housing enclosing an enclosed heat-dissipation air duct, and the computational heat dissipation structure; the computational heat dissipation structure is located in the enclosed heat-dissipation air duct. Since the space between the adjacent heating components of the disclosure is negatively correlated with the heat dissipation efficiency of the region where the adjacent heating components are located, i.e.

Abstract: The invention provides a full swing voltage conversion circuit. The full swing voltage conversion circuit comprises: an input terminal for inputting a first level signal; an output terminal for outputting a second level signal; a differential input unit for inverting the first level signal of the input terminal, and outputting a differential input signal; a conversion unit; and an output driving unit; wherein the full swing voltage conversion circuit further comprises an auxiliary pull-down unit between the input terminal and the conversion unit for receiving a feedback to improve capability of the conversion unit in recognizing the differential input signal, such that the full swing voltage conversion circuit of the invention can convert from inputting a low voltage to outputting a high voltage.

Abstract: A data compression method, comprising: obtaining a plurality of values of a parameter and an occurrence probability of each of the plurality of values (S101) comparing the occurrence probability with a predetermined threshold, wherein values with the occurrence probability less than the predetermined threshold are first set of values, and values with the occurrence probability greater than or equal to the predetermined threshold are second set of values (S102), performing pretreatment on the first set of values (S103), and encoding the second set of values and the pretreated first set of values (S104). By means of the data compression method, the maximum codeword length can be effectively reduced, so as to reduce the requirements of a code table to the storage space.

Abstract: The present invention discloses a series circuit and a computing device, including: a power supply terminal for providing voltage for a plurality of chips disposed on the computing device; a ground terminal disposed at one end of each of the plurality of chips relative to the power supply terminal; and a first connection line for separately connecting a first predetermined number of chips of the plurality of chips in series, wherein a communication line is connected between adjacent chips of the first predetermined number of chips, a portion of the communication line is connected to a target connection point, which is disposed on the first connection line and adapted to the adjacent chips, via a third connection line, and the voltage at the target connection point is greater than or equal to the minimum voltage required for communication between the adjacent chips.

Abstract: The invention provides a dynamic D flip-flop, and a data operation unit, a chip, a hash board and a computing device using the same. The dynamic D flip-flop comprises: an input terminal, an output terminal and at least one clock signal terminal; a latch unit for latching data of the input terminal and inversely transmitting the data under control of a clock signal; and an output driving unit for inverting and outputting the data received from the latch unit; wherein the latch unit outputs in high level, low level and high impedance states by means of a single element under control of a clock signal. Therefore, the invention can effectively reduce chip area, power consumption, and logic delay.

Abstract: Provided are an adaptive quantization method and apparatus, a device and medium. The method comprises: respectively performing a first quantization processing on a plurality of original input tensors to obtain an input tensor in a fixed-point number form, and calculating a quantization offset of the input tensor in the fixed-point number form (S102); calculating a comprehensive quantization offset corresponding to the plurality of original input tensors, and an adaptive quantization coefficient (S104); according to the adaptive quantization coefficient and the comprehensive quantization offset, performing a second quantization process on the input tensor in the fixed-point number form and the quantization offset to obtain a quantization result (S106). The method is helpful to improve the quantization accuracy, improve the performance of the convolutional neural network, and reduce the hardware power consumption and design difficulty.

Abstract: The invention provides a dynamic D flip-flop, and a data operation unit, a chip, a hash board and a computing device using the same. The dynamic D flip-flop comprises: an input terminal, an output terminal and at least one clock signal terminal; a first latch unit for transmitting data of the input terminal and latching the data under control of a clock signal; a second latch unit for latching data of the output terminal and inversely transmitting the data latched by the first latch unit under control of a clock signal; and an output driving unit for inverting and outputting the data received from the second latch unit; wherein the second latch unit outputs in high level, low level and high impedance states by means of a single element under control of a clock signal. Therefore, the invention can effectively reduce chip area, power consumption, and logic delay.

Abstract: A series circuit and a computing device includes a power supply terminal, a ground terminal and a first connection line for separately connecting a first predetermined number of chips of the plurality of chips in series. A communication line is connected between adjacent chips of the first predetermined number of chips. A portion of the communication line is connected to a target connection point, which is disposed on the first connection line and adapted to the adjacent chips, via a second connection line, and the voltage at the target connection point is greater than or equal to the minimum voltage required for communication between the adjacent chips.

Abstract: Disclosed in the present application are a convolutional neural network computing acceleration method and apparatus, a device, and a medium. The method at least comprises: quantizing an original input tensor and convolution kernel by using a first function to obtain an input tensor and convolution kernel in a fixed-point number form; computing respective quantization offsets of the input tensor and convolution kernel in the fixed-point number form by using a second function, wherein the first function and the second function comprise corresponding quantization scaling factors, and conversion logic for converting a floating-point number into a fixed-point number; computing a first convolution result of the input tensor and convolution kernel in the fixed-point number form according to the quantization offsets; and computing a second convolution result of the original input tensor and convolution kernel according to the quantization scaling factors and the first convolution kernel.

Abstract: The invention provides a full swing voltage conversion circuit. The full swing voltage conversion circuit comprises: an input terminal for inputting a first level signal; an output terminal for outputting a second level signal; a differential input unit for inverting the first level signal of the input terminal, and outputting a differential input signal; a conversion unit; and an output driving unit; wherein the full swing voltage conversion circuit further comprises an auxiliary pull-down unit between the input terminal and the conversion unit for receiving a feedback to improve capability of the conversion unit in recognizing the differential input signal, such that the full swing voltage conversion circuit of the invention can convert from inputting a low voltage to outputting a high voltage.