Patents by Inventor Naofumi Abiko
Naofumi Abiko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160322110Abstract: According to one embodiment, there is provided a semiconductor storage device including a memory cell array and a control circuit. The memory cell array has multiple memory cells connected to word lines and bit lines. The control circuit sets a value of a control voltage used to control voltages on the bit lines at a first value and, if receiving a first command including a change request to change the control voltage and including a to-be-changed-to second value, changes the value of the control voltage used to control the voltages on the bit lines from the first value to the second value, according to the change request.Type: ApplicationFiled: August 24, 2015Publication date: November 3, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Naofumi ABIKO, Yoshikazu HARADA
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Publication number: 20160260497Abstract: According to one embodiment, a device includes a memory cell array including memory cells and controller. The controller executes verification of second data in a first verify period in a first verify operation and verification of third data in a second verify period in the first verify operation. The controller excludes memory cells to be written first data from a target of the first verify operation at a first time in the first verify period and excludes memory cells to be written the second data from the target at a second time in the second verify period.Type: ApplicationFiled: September 4, 2015Publication date: September 8, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yoshikazu HARADA, Masahiro YOSHIHARA, Naofumi ABIKO
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Publication number: 20160189777Abstract: A semiconductor storage device has a memory string including a memory cell, a bit line electrically connected to one end of the memory string, and a sense amplifier electrically connected to the bit line. The sense amplifier has a first transistor, one end of which is connected to a first node on an electric current path of the bit line, and another end of which is electrically connected to a second node, a second transistor electrically connected between the second node and a sense node, and a third transistor, a gate of which is connected to the first node, and the third transistor being electrically connected between the second node and a third node whose voltage can be adjusted.Type: ApplicationFiled: March 7, 2016Publication date: June 30, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Masahiro YOSHIHARA, Naofumi ABIKO
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Patent number: 9070444Abstract: A semiconductor memory device includes a memory cell array including memory cells arranged therein. A first latch circuit temporarily holds data to perform a read operation and a write operation on the memory cell array. The second latch circuit temporarily holds a control signal. A control circuit controls the memory cell array, the first latch circuit and the second latch circuit. The control circuit limits an operation of the first latch circuit in a state after an operation on the memory cell array has been finished, and limits an operation of the second latch circuit based on a command supplied from external.Type: GrantFiled: July 23, 2013Date of Patent: June 30, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Naofumi Abiko, Masahiro Yoshihara, Akio Sugahara, Yoshikazu Harada
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Patent number: 9001582Abstract: A nonvolatile semiconductor memory device includes memory cells arranged into memory strings with word lines each connected to a different memory cell of the memory strings. The device also includes bit lines each connected to a different memory string and a column decoder connected to the bit lines. The column decoder includes sense amplifiers, data latches, and a data bus connecting sense amplifiers and data latches. The data bus is divided into at least two portions and includes a first portion connected to a second portion by a switch.Type: GrantFiled: March 4, 2013Date of Patent: April 7, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Tomofumi Fujimura, Naofumi Abiko
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Patent number: 8923074Abstract: A sense amplifier circuit is connected to a bit-line and senses and amplifies a signal read from a memory cell. A first data latch is connected to a sense amplifier via a first bus. A second data latch is connected to a second bus. A plurality of circuit groups are repeatedly provided in a first direction, each circuit group including one sense amplifier circuit and one first data latch. The second data latch is provided between the circuit groups and an input/output buffer.Type: GrantFiled: March 28, 2012Date of Patent: December 30, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Masahiro Yoshihara, Naofumi Abiko, Katsumi Abe
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Publication number: 20140269097Abstract: According to one embodiment, a non-volatile semiconductor memory device includes a memory cell array and a sense amplifier. The memory cell array includes a plurality of memory cell transistors. The sense amplifier reads data held in the memory cell transistors. The sense amplifier writes data to the memory cell transistors. The sense amplifier includes a first sense unit, a first operational unit, a second sense unit, and a second operational unit. The first sense unit includes a first sub-amplifier group and a first switch group. The second sense unit includes a second sub-amplifier group and a second switch group. The first sub-amplifier group is electrically connected to a first data bus. The second sub-amplifier group is electrically connected to a second data bus. The first operational unit is electrically connected to the first data bus and the second data bus.Type: ApplicationFiled: September 9, 2013Publication date: September 18, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroyuki KAGA, Masahiro Yoshihara, Naofumi Abiko, Yoshikazu Harada
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Publication number: 20140241072Abstract: A semiconductor memory device includes a memory cell array including memory cells arranged therein. A first latch circuit temporarily holds data to perform a read operation and a write operation on the memory cell array. The second latch circuit temporarily holds a control signal. A control circuit controls the memory cell array, the first latch circuit and the second latch circuit. The control circuit limits an operation of the first latch circuit in a state after an operation on the memory cell array has been finished, and limits an operation of the second latch circuit based on a command supplied from external.Type: ApplicationFiled: July 23, 2013Publication date: August 28, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Naofumi ABIKO, Masahiro Yoshihara, Akio Sugahara, Yoshikazu Harada
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Patent number: 8599613Abstract: According to one embodiment, a nonvolatile semiconductor memory includes a memory cell array including memory cells of a first unit in which read and write are parallelly performed, n (n is a natural number of not less than 2) sense amplifiers, n detection circuits corresponding to the n sense amplifiers, an accumulator configured to divide the first unit data read from the memory cell array into z (z is a natural number) second unit data and accumulate a fail bit for which the write is incomplete for the second unit data, and a control circuit configured to control an operation of detecting the fail bit after the write.Type: GrantFiled: March 23, 2012Date of Patent: December 3, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Naofumi Abiko, Masahiro Yoshihara
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Publication number: 20130250684Abstract: A nonvolatile semiconductor memory device includes memory cells arranged into memory strings with word lines each connected to a different memory cell of the memory strings. The device also includes bit lines each connected to a different memory string and a column decoder connected to the bit lines. The column decoder includes sense amplifiers, data latches, and a data bus connecting sense amplifiers and data latches. The data bus is divided into at least two portions and includes a first portion connected to a second portion by a switch.Type: ApplicationFiled: March 4, 2013Publication date: September 26, 2013Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tomofumi FUJIMURA, Naofumi ABIKO
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Patent number: 8472248Abstract: According to one embodiment, a semiconductor memory includes a memory cell array which includes memory cells, the memory cells being arranged along a row direction and a column direction and storing data respectively corresponding to thresholds, a row control circuit which controls a row of the memory cell array, and a column control circuit which includes a control unit, the control unit generating a signal to control elements corresponding to column of the memory cell array in accordance with a pointer corresponding to an external address signal.Type: GrantFiled: September 18, 2011Date of Patent: June 25, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Hiroyuki Kaga, Masahiro Yoshihara, Naofumi Abiko
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Patent number: 8363486Abstract: According to one embodiment, in a nonvolatile semiconductor memory device, a data latch circuit which is connected to a sense amplifier circuit controls a data writing operation and a data reading operation to and from a nonvolatile memory cell array through a data bus, and outputs the stored data to the data bus when the sense amplifier circuit performs the data writing operation. The data latch circuit is provided with two nodes respectively storing and outputting normal data and reverse data which are connected to the data bus.Type: GrantFiled: September 17, 2010Date of Patent: January 29, 2013Assignee: Kabushiki Kaisha ToshibaInventor: Naofumi Abiko
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Publication number: 20120250409Abstract: According to one embodiment, a semiconductor memory includes a memory cell array which includes memory cells, the memory cells being arranged along a row direction and a column direction and storing data respectively corresponding to thresholds, a row control circuit which controls a row of the memory cell array, and a column control circuit which includes a control unit, the control unit generating a signal to control elements corresponding to column of the memory cell array in accordance with a pointer corresponding to an external address signal.Type: ApplicationFiled: September 18, 2011Publication date: October 4, 2012Inventors: Hiroyuki KAGA, Masahiro Yoshihara, Naofumi Abiko
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Publication number: 20120250424Abstract: A sense amplifier circuit is connected to a bit-line and senses and amplifies a signal read from a memory cell. A first data latch is connected to a sense amplifier via a first bus. A second data latch is connected to a second bus. A plurality of circuit groups are repeatedly provided in a first direction, each circuit group comprising one sense amplifier circuit and one first data latch. The second data latch is provided between the circuit groups and an input/output buffer.Type: ApplicationFiled: March 28, 2012Publication date: October 4, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Masahiro YOSHIHARA, Naofumi Abiko, Katsumi Abe
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Publication number: 20120250411Abstract: According to one embodiment, a nonvolatile semiconductor memory includes a memory cell array including memory cells of a first unit in which read and write are parallelly performed, n (n is a natural number of not less than 2) sense amplifiers, n detection circuits corresponding to the n sense amplifiers, an accumulator configured to divide the first unit data read from the memory cell array into z (z is a natural number) second unit data and accumulate a fail bit for which the write is incomplete for the second unit data, and a control circuit configured to control an operation of detecting the fail bit after the write.Type: ApplicationFiled: March 23, 2012Publication date: October 4, 2012Inventors: Naofumi ABIKO, Masahiro Yoshihara
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Patent number: 8203885Abstract: According to an embodiment, a nonvolatile semiconductor memory system includes: a nonvolatile semiconductor memory; and a memory controller having: a memory interface unit that inputs commands to the nonvolatile semiconductor memory and inputs or outputs data between the nonvolatile semiconductor memory; a memory that stores writing information indicating a memory cell transistor that is written the latest in each of the NAND cell units; and a processor that sets a read voltage based on the writing information to read out data from the memory cell transistors connected to a first word line; wherein a row controller is configured to set a plurality of levels of the read voltage to be applied to the first word line, with respect to one threshold for discriminating data stored in a memory cell transistors.Type: GrantFiled: July 8, 2011Date of Patent: June 19, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Naofumi Abiko, Takuya Futatsuyama
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Publication number: 20120002469Abstract: A nonvolatile semiconductor memory device according to an embodiment includes: a memory cell array including a plurality of memory cells selected by word lines and bit lines, each memory cell being capable of storing N-bit data, a set of n-th bits of a plurality of memory cells selected by one of the word lines constituting an n-th physical page, and a predetermined number of the bit lines constituting one column; and a data writing unit that divides each of first to N-th input data of the length of the physical page or less input from the outside into unit data of the length of the column, changes at least a portion of the order of unit data of the first to N-th input data of a predetermined column in the predetermined column before data writing, and performs writing.Type: ApplicationFiled: March 18, 2011Publication date: January 5, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Akihiro IMAMOTO, Naofumi Abiko
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Publication number: 20110267884Abstract: According to an embodiment, a nonvolatile semiconductor memory system includes: a nonvolatile semiconductor memory; and a memory controller having: a memory interface unit that inputs commands to the nonvolatile semiconductor memory and inputs or outputs data between the nonvolatile semiconductor memory; a memory that stores writing information indicating a memory cell transistor that is written the latest in each of the NAND cell units; and a processor that sets a read voltage based on the writing information to read out data from the memory cell transistors connected to a first word line; wherein a row controller is configured to set a plurality of levels of the read voltage to be applied to the first word line, with respect to one threshold for discriminating data stored in a memory cell transistors.Type: ApplicationFiled: July 8, 2011Publication date: November 3, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: NAOFUMI ABIKO, TAKUYA FUTATSUYAMA
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Patent number: 8009480Abstract: According to an embodiment, a nonvolatile semiconductor memory system includes: a nonvolatile semiconductor memory; and a memory controller having: a memory interface unit that inputs commands to the nonvolatile semiconductor memory and inputs or outputs data between the nonvolatile semiconductor memory; a memory that stores writing information indicating a memory cell transistor that is written the latest in each of the NAND cell units; and a processor that sets a read voltage based on the writing information to read out data from the memory cell transistors connected to a first word line; wherein a row controller is configured to set a plurality of levels of the read voltage to be applied to the first word line, with respect to one threshold for discriminating data stored in a memory cell transistors.Type: GrantFiled: December 3, 2009Date of Patent: August 30, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Naofumi Abiko, Takuya Futatsuyama
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Publication number: 20110141814Abstract: According to one embodiment, in a nonvolatile semiconductor memory device, a data latch circuit which is connected to a sense amplifier circuit controls a data writing operation and a data reading operation to and from a nonvolatile memory cell array through a data bus, and outputs the stored data to the data bus when the sense amplifier circuit performs the data writing operation. The data latch circuit is provided with two nodes respectively storing and outputting normal data and reverse data which are connected to the data bus.Type: ApplicationFiled: September 17, 2010Publication date: June 16, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Naofumi ABIKO