Patents by Inventor Naoki Kimura
Naoki Kimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220291868Abstract: A memory system of an embodiment is connectable to a host and includes a nonvolatile memory and a memory controller. The memory controller includes: a signal line which transfers a signal sent from the host; a resistance element disposed between and electrically connected to the signal line and a wiring line given a reference potential of the memory system; a switching element connected serially to the resistance element and capable of switching a connection between the signal line and the wiring line; and a control circuit which controls the switching element to switch the connection between the signal line and the wiring line from a connected state to a disconnected state, when a change from a first potential to a second potential occurs on the signal line or when a change from the second potential to the first potential occurs on the signal line.Type: ApplicationFiled: September 8, 2021Publication date: September 15, 2022Applicant: Kioxia CorporationInventors: Naoki KIMURA, Junya KISHIKAWA
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Publication number: 20220139469Abstract: A memory system includes a connector through which power for the memory system is to be supplied from an external device, a controller, a nonvolatile memory device, a power source circuit connected to the controller and the nonvolatile memory device by power lines through which power is supplied to the controller and the nonvolatile memory device, and a power source control circuit that receives a supply of power from the external device through the connector and supplies the power to the power control circuit. The power source control circuit is configured to detect using a divided voltage of a voltage of the power supplied thereto, that the voltage of the power supplied thereto is higher than a predetermined voltage and interrupt the power supplied to the power control circuit if the voltage of the power supplied thereto is higher than the predetermined voltage.Type: ApplicationFiled: January 18, 2022Publication date: May 5, 2022Inventor: Naoki KIMURA
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Publication number: 20220118895Abstract: A wheel loader representing a work vehicle includes an operator's seat, an armrest, and a seat operation portion. The armrest is provided lateral to the operator's seat. The seat operation portion controls a position or a posture of the operator's seat. The seat operation portion is attached to the armrest.Type: ApplicationFiled: October 17, 2019Publication date: April 21, 2022Applicant: KOMATSU LTD.Inventors: Akihiro KOSHI, Masahiko HAMAGUCHI, Hirofumi WADA, Naoki KIMURA
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Publication number: 20220122640Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.Type: ApplicationFiled: December 30, 2021Publication date: April 21, 2022Applicant: Kioxia CorporationInventors: Masato SUGITA, Naoki KIMURA, Daisuke KIMURA
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Publication number: 20220089770Abstract: In a non-limiting embodiment, isolated antibodies that bind to any of the following proteins are provided: XPR1, NOX1, MARVELD3 isoform 1, MARVELD3 isoform 2, SPINT2, MANSC1, SLC12A2, CDCP1, SEZ6L2, FLVCR1, SLC7A5, STEAP1, MMP14, TNFRSF21, and TMPRSS4.Type: ApplicationFiled: January 24, 2020Publication date: March 24, 2022Inventors: Junichi NEZU, Tatsushi KODAMA, Mayumi HOSHINO, Naoki KIMURA, Kohji NAGANO, Kuniyasu KATO, Yukari YOKOTA
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Patent number: 11258195Abstract: According to one embodiment, a storage device is disclosed. The storage device includes a substrate, a first connector provided on the substrate and including a notch, and a nonvolatile memory provided on the substrate. The storage device further includes a first conductive part provided on the first connector and being adjacent to the notch.Type: GrantFiled: September 11, 2019Date of Patent: February 22, 2022Assignee: Kioxia CorporationInventor: Naoki Kimura
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Patent number: 11257548Abstract: A memory system includes a connector through which power for the memory system is to be supplied from an external device, a controller, a nonvolatile memory device, a power source circuit connected to the controller and the nonvolatile memory device by power lines through which power is supplied to the controller and the nonvolatile memory device, and a power source control circuit that receives a supply of power from the external device through the connector and supplies the power to the power control circuit. The power source control circuit is configured to detect using a divided voltage of a voltage of the power supplied thereto, that the voltage of the power supplied thereto is higher than a predetermined voltage and interrupt the power supplied to the power control circuit if the voltage of the power supplied thereto is higher than the predetermined voltage.Type: GrantFiled: August 27, 2018Date of Patent: February 22, 2022Assignee: KIOXIA CORPORATIONInventor: Naoki Kimura
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Patent number: 11252817Abstract: A printed wiring board includes first, second, and third wiring layers, first and second insulating members, and first and second vias. The first wiring layer includes a recognition mark and a first wiring on a first surface. The second wiring layer includes a first pad and a second wiring. The third wiring layer includes a third wiring. The first via penetrates the first insulating member and electrically connects the recognition mark to the first pad. The second via penetrates the second insulating member and electrically connects the first pad to the third wiring. The first pad and the first and second vias are in a region within an outer perimeter of the recognition mark when viewed from a direction orthogonal to the first surface.Type: GrantFiled: February 24, 2021Date of Patent: February 15, 2022Assignee: KIOXIA CORPORATIONInventors: Naoki Kimura, Hiroaki Komaki
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Patent number: 11244708Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.Type: GrantFiled: October 22, 2020Date of Patent: February 8, 2022Assignee: Kioxia CorporationInventors: Masato Sugita, Naoki Kimura, Daisuke Kimura
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Publication number: 20210340727Abstract: A wheel loader representing a work vehicle includes an operator's seat, a console, and an armrest. The console includes an operation portion. The console is provided lateral to the operator's seat. The armrest includes an upper surface. The armrest is provided lateral to the operator's seat and in the rear of the operation portion. The armrest operates independently of the console such that a rear end of the upper surface is laterally displaced in a top view.Type: ApplicationFiled: October 17, 2019Publication date: November 4, 2021Applicant: KOMATSU LTD.Inventors: Akihiro KOSHI, Masahiko HAMAGUCHI, Hirofumi WADA, Naoki KIMURA
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Publication number: 20210296300Abstract: According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.Type: ApplicationFiled: June 9, 2021Publication date: September 23, 2021Applicant: Toshiba Memory CorporationInventors: Hayato MASUBUCHI, Naoki KIMURA, Manabu MATSUMOTO, Toyota MORIMOTO
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Publication number: 20210286743Abstract: A memory system includes a connector including a terminal, and a controller configured to perform a single-line bidirectional communication with a host via a signal line connected to the terminal. A format of a signal communicated via the single-line bidirectional communication includes a start pulse at a first level, a stop pulse at a second level, data pulses at the second level, and division pulses at the first level. The data pulses are after the start pulse but before the stop pulse. Each of the data pulses has a pulse width corresponding to a data value represented thereby. The division pulses have a uniform pulse width. A pulse width of the start pulse is greater than the uniform pulse width of the divisional pulses. A pulse width of the stop pulse is greater than any pulse width of the data pulses.Type: ApplicationFiled: August 27, 2020Publication date: September 16, 2021Inventor: Naoki KIMURA
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Patent number: 11063031Abstract: According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.Type: GrantFiled: February 25, 2020Date of Patent: July 13, 2021Assignee: Toshiba Memory CorporationInventors: Hayato Masubuchi, Naoki Kimura, Manabu Matsumoto, Toyota Morimoto
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Publication number: 20210054076Abstract: The present inventors discovered novel multispecific antigen-binding molecules with excellent cellular cytotoxicity and high stability, which comprise a first domain comprising a first antibody variable region that binds to Claudin 6, a second domain comprising a second antibody variable region that binds to T cell receptor complex. Since the molecules of the present invention show a strong cytotoxicity against cells and tissues expressing Claudin 6, it is possible to produce novel pharmaceutical compositions comprising the multispecific antigen-binding molecules for treating or preventing various cancers.Type: ApplicationFiled: January 4, 2019Publication date: February 25, 2021Inventor: Naoki KIMURA
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Publication number: 20210043235Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.Type: ApplicationFiled: October 22, 2020Publication date: February 11, 2021Applicant: Toshiba Memory CorporationInventors: Masato SUGITA, Naoki Kimura, Daisuke Kimura
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Patent number: 10847190Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.Type: GrantFiled: January 8, 2020Date of Patent: November 24, 2020Assignee: Toshiba Memory CorporationInventors: Masato Sugita, Naoki Kimura, Daisuke Kimura
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Publication number: 20200301617Abstract: According to one embodiment, a storage device is disclosed. The storage device includes a substrate, a first connector provided on the substrate and including a notch, and a nonvolatile memory provided on the substrate. The storage device further includes a first conductive part provided on the first connector and being adjacent to the notch.Type: ApplicationFiled: September 11, 2019Publication date: September 24, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventor: Naoki KIMURA
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Publication number: 20200194414Abstract: According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.Type: ApplicationFiled: February 25, 2020Publication date: June 18, 2020Applicant: Toshiba Memory CorporationInventors: Hayato MASUBUCHI, Naoki KIMURA, Manabu MATSUMOTO, Toyota MORIMOTO
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Patent number: 10656692Abstract: According to one embodiment, a memory system includes a volatile memory, a power supply circuit, and a controller. The power supply circuit includes a first power supply path in which power supplied from a host device is supplied to the volatile memory, a second power supply path in which the power is supplied from the internal power supply to the volatile memory, and a switching device that switches between the first power supply path and the second power supply path. In response to an instruction for a transition to a low power consumption mode received from the host device, the controller outputs, to the switching device, an instruction to switch the power supply circuit from the first power supply path to the second power supply path.Type: GrantFiled: September 15, 2017Date of Patent: May 19, 2020Assignee: Toshiba Memory CorporationInventor: Naoki Kimura
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Publication number: 20200143848Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.Type: ApplicationFiled: January 8, 2020Publication date: May 7, 2020Applicant: Toshiba Memory CorporationInventors: Masato SUGITA, Naoki KIMURA, Daisuke KIMURA