Patents by Inventor Naoki Kimura

Naoki Kimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10607979
    Abstract: According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: March 31, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Hayato Masubuchi, Naoki Kimura, Manabu Matsumoto, Toyota Morimoto
  • Patent number: 10593617
    Abstract: According to one embodiment, a semiconductor device includes a first board including a plurality of terminals, a semiconductor chip flip-chip mounted to the first board, and an insulating layer covering the first board and the semiconductor chip. The plurality of terminals include at least one first terminal electrically connected to the semiconductor chip, and at least one second terminal that is not connected to the semiconductor chip, wherein the at least one second terminal is not covered by the insulating layer.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: March 17, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hiroshi Ashikaga, Naoki Kimura
  • Patent number: 10566033
    Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: February 18, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Masato Sugita, Naoki Kimura, Daisuke Kimura
  • Patent number: 10541382
    Abstract: Provided is an electroluminescent device that emits light of a single color and includes a plurality of functional layers, in which an absorption peak is included in the emission wavelength and at least one absorption peak is included in a complementary color region of an emission wavelength in the range of 380 nm to 780 nm, an absolute value of a deviation (?uv) of a color coordinate of front reflected light at the time of white color illumination from a blackbody locus is below 0.02, and a refractive index and a film thickness of each of the plurality of functional layers are determined to satisfy the formula D(?)?D(0)cos ? (0????D?60 degrees) when an angle dependence of emission intensity is defined as D(?).
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: January 21, 2020
    Assignee: KONICA MINOLTA, INC.
    Inventors: Kou Osawa, Koujirou Sekine, Naoki Kimura
  • Publication number: 20190326275
    Abstract: According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.
    Type: Application
    Filed: July 3, 2019
    Publication date: October 24, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Hayato MASUBUCHI, Naoki KIMURA, Manabu MATSUMOTO, Toyota MORIMOTO
  • Publication number: 20190295664
    Abstract: A memory system includes a connector through which power for the memory system is to be supplied from an external device, a controller, a nonvolatile memory device, a power source circuit connected to the controller and the nonvolatile memory device by power lines through which power is supplied to the controller and the nonvolatile memory device, and a power source control circuit that receives a supply of power from the external device through the connector and supplies the power to the power control circuit. The power source control circuit is configured to detect using a divided voltage of a voltage of the power supplied thereto, that the voltage of the power supplied thereto is higher than a predetermined voltage and interrupt the power supplied to the power control circuit if the voltage of the power supplied thereto is higher than the predetermined voltage.
    Type: Application
    Filed: August 27, 2018
    Publication date: September 26, 2019
    Inventor: Naoki KIMURA
  • Publication number: 20190279686
    Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.
    Type: Application
    Filed: May 28, 2019
    Publication date: September 12, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Masato Sugita, Naoki Kimura, Daisuke Kimura
  • Patent number: 10388640
    Abstract: According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.
    Type: Grant
    Filed: November 24, 2017
    Date of Patent: August 20, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hayato Masubuchi, Naoki Kimura, Manabu Matsumoto, Toyota Morimoto
  • Patent number: 10381587
    Abstract: A light emitting apparatus includes: a sealing member (20) forming a sealing region sealing a planar light emitting unit; and a wiring member (51) including a conductive unit (61) electrically connected to the planar light emitting unit and extending from the sealing region to an outside. The sealing member (20) has a drawing port opened at a periphery of the sealing member for drawing the wiring member (51) to the outside. The wiring member (51) includes: an internal wiring portion (71) in which the conductive unit (61) is disposed in the sealing region; an external wiring portion (72) in which the conductive unit (61) is disposed in the outside; and a boundary wiring portion (73) in which the conductive unit (61) is disposed in the drawing port and which has a smaller thickness than the internal wiring portion (71) and/or the external wiring portion (72).
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: August 13, 2019
    Assignee: KONICA MINOLTA, INC.
    Inventors: Yasushi Tanijiri, Masatoshi Yoneyama, Junya Wakahara, Mitsuyoshi Naito, Naoki Kimura, Kenji Hiraiwa
  • Patent number: 10361524
    Abstract: An interface includes a connector that is physically and electrically connectable to a device conforming to a first interface standard and a device conforming to a second interface standard, and an interface circuit including a signal line extending to a terminal of the connector, a coupling capacitor disposed on the signal line, and a switch having a first end electrically connected to a first terminal of the coupling capacitor and a second end electrically connected to a second terminal of the coupling capacitor. The switch is turned on when the connector is connected to a device conforming to the first interface standard so that a signal bypasses the coupling capacitor and is transmitted through the switch and turned off when the connector is connected to a device conforming to the second interface standard so that the signal is transmitted through the coupling capacitor.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: July 23, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Naoki Kimura
  • Patent number: 10347908
    Abstract: A lithium ion secondary battery having a negative electrode includes a negative electrode active material containing at least one of two material of silicon and a silicon compound and carbon, a weight mixing ratio of at least one of two material of the silicon and the silicon compound and the carbon is 20:80 to 50:50, when D90 of particles of at least one of two material of the silicon and the silicon compound is x, D50 of particles of the carbon is y, and the weight mixing ratio of the carbon is z, y??1.17x+0.45z is satisfied, the x is between 2 ?m and 10 ?m, the y is between 10 ?m and 23 ?m, and the z is between 50% and 80% by weight, and a coefficient of expansion when the negative electrode is fully charged is 110% or more and 140% or less.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: July 9, 2019
    Assignee: HITACHI, LTD.
    Inventors: Seogchul Shin, Naoki Kimura, Eiji Seki
  • Patent number: 10340008
    Abstract: In one embodiment, an electronic device includes a power supply circuit that has a first switch circuit between a power supply line and a ground potential. The first switch circuit connects the power supply line to the ground potential upon receipt of a control signal that is supplied when a supply of power on the power supply line is cut off. A capacitor is connected between the power supply line and the ground potential. A second switch circuit is between the capacitor and the power supply line. The second switch circuit is configured to disconnect the capacitor from the power supply line upon receipt of the first control signal. A controller circuit is configured to supply the first control signal when the supply of power on the power supply line is cut off.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: July 2, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takuma Kawamura, Naoki Kimura
  • Patent number: 10339981
    Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: July 2, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Masato Sugita, Naoki Kimura, Daisuke Kimura
  • Patent number: 10299381
    Abstract: According to one embodiment, an electronic device includes a substrate including a first face, a plurality of first conductors on the first face, a plurality of second conductors on the first face, and a first electronic component mounted on the first face, and including a first terminal connected to the plurality of first conductors, and a second terminal connected to the plurality of second conductors.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: May 21, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Naoki Kimura, Tatsuro Hiruta
  • Patent number: 10242716
    Abstract: A semiconductor device includes a substrate, a nonvolatile semiconductor memory disposed on a surface of the substrate, and a controller disposed on a surface of the controller. The substrate has a slit on an edge on which interface connection terminals are formed, a ground pattern, first and second wiring patterns that are electrically connected to the ground pattern and extend in a direction in which the slit extends, and a through hole that is formed between the first and second wiring patterns and is large enough along a dimension between the first and second wiring patterns to span substantially all of the spacing between the first and second wiring patterns.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: March 26, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Naoki Kimura
  • Publication number: 20190088332
    Abstract: In one embodiment, an electronic device includes a power supply circuit that has a first switch circuit between a power supply line and a ground potential. The first switch circuit connects the power supply line to the ground potential upon receipt of a control signal that is supplied when a supply of power on the power supply line is cut off. A capacitor is connected between the power supply line and the ground potential. A second switch circuit is between the capacitor and the power supply line. The second switch circuit is configured to disconnect the capacitor from the power supply line upon receipt of the first control signal. A controller circuit is configured to supply the first control signal when the supply of power on the power supply line is cut off.
    Type: Application
    Filed: March 2, 2018
    Publication date: March 21, 2019
    Inventors: Takuma KAWAMURA, Naoki KIMURA
  • Publication number: 20190088583
    Abstract: According to one embodiment, a semiconductor device includes a first board including a plurality of terminals, a semiconductor chip flip-chip mounted to the first board, and an insulating layer covering the first board and the semiconductor chip. The plurality of terminals include at least one first terminal electrically connected to the semiconductor chip, and at least one second terminal that is not connected to the semiconductor chip, wherein the at least one second terminal is not covered by the insulating layer.
    Type: Application
    Filed: March 2, 2018
    Publication date: March 21, 2019
    Inventors: Hiroshi ASHIKAGA, Naoki KIMURA
  • Publication number: 20190067613
    Abstract: A light emitting apparatus includes: a sealing member (20) forming a sealing region sealing a planar light emitting unit; and a wiring member (51) including a conductive unit (61) electrically connected to the planar light emitting unit and extending from the sealing region to an outside. The sealing member (20) has a drawing port opened at a periphery of the sealing member for drawing the wiring member (51) to the outside. The wiring member (51) includes: an internal wiring portion (71) in which the conductive unit (61) is disposed in the sealing region; an external wiring portion (72) in which the conductive unit (61) is disposed in the outside; and a boundary wiring portion (73) in which the conductive unit (61) is disposed in the drawing port and which has a smaller thickness than the internal wiring portion (71) and/or the external wiring portion (72).
    Type: Application
    Filed: November 14, 2016
    Publication date: February 28, 2019
    Applicant: Konica Minolta, Inc.
    Inventors: Yasushi TANIJIRI, Masatoshi YONEYAMA, Junya WAKAHARA, Mitsuyoshi NAITO, Naoki KIMURA, Kenji HIRAIWA
  • Publication number: 20190036081
    Abstract: Provided is an electroluminescent device that emits light of a single color and includes a plurality of functional layers, in which an absorption peak is included in the emission wavelength and at least one absorption peak is included in a complementary color region of an emission wavelength in the range of 380 nm to 780 nm, an absolute value of a deviation (?uv) of a color coordinate of front reflected light at the time of white color illumination from a blackbody locus is below 0.02, and a refractive index and a film thickness of each of the plurality of functional layers are determined to satisfy the formula D(?)?D(0)cos ? (0????D?60 degrees) when an angle dependence of emission intensity is defined as D(?).
    Type: Application
    Filed: August 29, 2016
    Publication date: January 31, 2019
    Inventors: KOU OSAWA, KOUJIROU SEKINE, NAOKI KIMURA
  • Publication number: 20180358612
    Abstract: A lithium ion secondary battery that can inhibit an electrolytic solution in the lithium ion secondary battery using a negative electrode active material containing Si from decomposing, improve cycle characteristics, and obtain both a high energy density and a longer service life. A lithium ion secondary battery contains a negative electrode, a positive electrode, a separator installed between the negative and positive electrodes, and an electrolytic solution; the electrolytic solution contains fluoroethylene carbonate; the negative electrode has a negative electrode active material having particles containing silicon and particles containing carbon and a film being formed over a surface of the negative electrode active material and containing fluorine; and a surface area of the particles containing silicon and a content of fluorine contained in the film satisfy the following Formula 1: 0.005 g/m2?(Fluorine content (g) contained in film)/(Surface area (m2) of particles containing silicon)?0.015 g/m2.
    Type: Application
    Filed: October 31, 2016
    Publication date: December 13, 2018
    Applicant: HITACHI, LTD.
    Inventors: Eiji SEKI, Naoki KIMURA, Seogchul SHIN