Abstract: A transmission system for transmitting a first differential signal includes a transmitter, a transmission path, and a receiver. The transmitter transmits the first differential signal and a second differential signal. The transmission path transfers the first differential signal and the second differential signal. The receiver receives the first differential signal and the second differential signal. The transmitter includes a generator circuit and a switch. The generator circuit generates the second differential signal lower in baud rate than the first differential signal. The switch selects between the second differential signal and the first differential signal to output the selected differential signal to the transmission path. The receiver includes a detector circuit and a corrector circuit. The detector circuit detects a skew of the second differential signal. The corrector circuit corrects a skew of the first differential signal based by the detected skew of the second differential signal.

Abstract: A CPU 200 selects one or multiple image data GD to be pasted on ornamental image data among plurality of input image data GD and gains image processing control information GI related to the selected image data GD. The CPU 200 selects desired ornamental image data FD and gains layout control information LI related to the selected ornamental image data FD. The CPU 200 also reads image quality adjustment information GC included in the layout control information LI. The CPU 200 executes image quality adjustment of each of the selected image data GD with the image processing control information GI and the image quality adjustment information GC. The CPU 200 pastes the respective image data GD, which have gone through the image quality adjustment, on the ornamental image data FD according to the layout control information LI to generate resulting output image data.

Abstract: A receiving/processing unit receives signals parallelized by a parallelizing unit, and executes a frame process including frame synchronization process on the signals. A phase comparing circuit and a phase judging circuit judge whether a bit delay is present based on a phase difference between a phase of a clock signal at a clock/data recovering unit and a phase of a clock signal at the parallelizing unit. The receiving/processing unit includes a logic processing circuit that executes a bit delay process based on a result of judgment by the phase comparing circuit and the phase judging circuit.

Abstract: A data processing circuit includes: a first circuit part having a first synchronization signal; a second circuit part having a second synchronization signal, and receiving a data signal and the first synchronization signal from the first circuit part; a phase comparing part carrying out phase comparison between the second synchronization signal and the first synchronization signal in the second circuit part; and a control part controlling a phase of the first synchronization signal based on a comparison result of the phase comparing part.

Abstract: A CPU selects multiple objective image data to be pasted on ornamental image data, analyzes the selected multiple objective image data, and rates the image qualities of the respective image data. The CPU specifies the number of plural layout locations included in the ornamental image data and the priority order of the plural layout locations, and allocates the multiple objective image data to the plural layout locations in the ornamental image data, based on the specified priority order and the ratings of the multiple objective image data. The CPU executes image quality adjustment with regard to the multiple objective image data allocated to the plural layout locations and pastes the quality-adjusted image data on the ornamental image data according to layout control information, so as to generate resulting output image data.

Abstract: A receiving apparatus receives parallel data signals including a plurality of channels from a transmitting apparatus. The receiving apparatus includes a receiver, a detector, and a switch. The receiver receives the parallel data signals. The detector detects a first skew between channels within the receiving apparatus, and a second skew between channels prior to reception by the receiver. The switch interchanges the plurality of channels of the parallel data signals so as to reduce a total skew as a sum of the first skew and the second skew.

Abstract: In a circuit suppressing jitters without a synchronizing clock signal and an increase of a circuit scale, input data is regenerated by a data regeneration circuit in a broadband, a predetermined signal pattern which generates phase deviations exceeding a predetermined value is detected from the data regenerated by the data regeneration circuit by a pattern detection circuit, a reverse phase deviation signal having reverse phase deviations of phase deviations corresponding to the predetermined signal pattern is generated by a reverse phase deviation generating circuit, and an output signal of the data regeneration circuit is canceled by a phase deviation correcting circuit with the reverse phase deviation signal.

Abstract: A phase shift unit provides a prescribed phase difference (?/2, for example) between a pair of optical signals transmitted via a pair of arms constituting a data modulation unit. A low-frequency signal f0 is superimposed on one of the optical signals. A signal of which phase is shifted by ?/2 from the low-frequency signal f0 is superimposed on the other optical signal. A pair of the optical signals is coupled, and a part of which is converted into an electrical signal by a photodiode. 2f0 component contained in the electrical signal is extracted. Bias voltage provided to the phase shift unit is controlled by feedback control so that the 2f0 component becomes the minimum.

Abstract: A CPU extracts ornamental image data and layout control information from an ornamental image file FF. When the layout control information does not include characteristic values, the CPU analyzes the ornamental image data to acquire characteristic values representing a tendency of image quality of the ornamental image data. The CPU may additionally compute correction rates for correcting values of image quality-relating parameters of objective image data from the acquired characteristic values of the ornamental image data. The CPU writes either the acquired characteristic values or the computed correction rates into the layout control information. The layout control information including the acquired characteristic values or the computed correction rates is output together with the ornamental image data in the form of the ornamental image file FF.

Abstract: An image-processing device adapted to the increased types of color printers without excessive manpower includes a common color correction unit, which carries out a conversion (color correction or customization) common to the models of color printers. Therefore, the method for conversion does not need to be changed depending on the type of color printer. As a result, color correction mode-adapted LUTs, stored color correction LUTs, and light source correction LUTs needed for the common color correction unit do not increase even if the models of color printers increase, and common LUTs can be used. Consequently, the manpower needed to fabricate the color correction mode-adapted LUTs, stored color correction LUTs, and light source correction LUTs does not increase even if the models of printers increase, so that the image-processing device can be adapted to an increase of the models of color printers without excessive manpower.

Abstract: A CPU 200 obtains and analyzes one or multiple image data GD, which are to be laid out on ornamental image data FD. The CPU 200 also obtains and analyzes desired ornamental image data FD to acquire a color distribution characteristic (representative color Fc). The CPU 200 sets an analyzed correction level according to the result of the analysis of the image data GD and modifies the analyzed correction level based on the acquired color distribution characteristic, so as to set a modified color balance correction level. The CPU 200 adjusts the color balance of the image data GD with the modified color balance correction level and pastes the color balance-adjusted image data GD onto the ornamental image data FD according to layout control information LI to generate output image data.

Abstract: In image processing according to the prior art, the important part of photographic image data (referred to herein as the object) could not be determined and therefore required human participation. A computer 21 which is the core of image processing calculates an edginess which is an image variation from a differential value of data for adjacent picture elements in a step SA110, and determines object picture elements by selecting only images with a large variation in steps SA120, SA130. As optimum parameters for contrast correction and lightness compensation are calculated from image data for object picture elements in steps SA310-SA330, image processing indicators based on object picture elements are determined, and optimum image processing can be performed automatically.

Abstract: A CPU 200 extracts ornamental image data and layout control information from an ornamental image file FF. When the layout control information does not include characteristic values, the CPU 200 analyzes the ornamental image data to acquire characteristic values representing a tendency of image quality of the ornamental image data. The CPU 200 may additionally compute correction rates for correcting values of image quality-relating parameters of objective image data from the acquired characteristic values of the ornamental image data. The CPU 200 writes either the acquired characteristic values or the computed correction rates into the layout control information. The layout control information including the acquired characteristic values or the computed correction rates is output together with the ornamental image data in the form of the ornamental image file FF.

Abstract: In a receiver, a skew detector detects a skew between two synchronization symbols having different wavelengths among synchronization symbols included in received signals. A skew rough adjustment calculator calculates a delay compensation amount for each received signal based on the skew and a signal delay characteristic in a transmission path. A variable delay processor deskews the received signals based on the delay compensation amount.

Abstract: Scores are calculated for each of a plurality of preselected evaluation items for each image, and the plurality of scores are weighted and combined to produce combined scores. Then a plurality of candidate images are selected and displayed from a group of images based on these combined scores. A user selects one or more images to be processed from these candidate images, and the degrees of correlation between user selected images and evaluation items are found based on the scores for a plurality of evaluation items in the images selected for processing. Then the weightings of evaluation items having high degrees of correlation are increased.

Abstract: An optical signal reception device is disclosed that receives and demodulates an optical signal modulated by DQPSK and performs logical inversion and other controls to transit to the object reception state.

Abstract: A method of extracting at least a portion of moving image data from supplied moving image data is provided. The method includes (a) a moving image evaluation step of generating moving image evaluation data by evaluating the supplied moving image data, the evaluation being chronologically performed based on a prescribed condition, (b) a moving image data extraction step of extracting the at least a portion of moving image data from the supplied moving image data based on the moving image evaluation data, and (c) a moving image data classification step of classifying the extracted moving image data into a plurality of classes based on the moving image evaluation data.

Abstract: A communication apparatus in accordance with an embodiment comprises a reception unit configured to demodulate a received signal to output a first demodulated signal in dependence on a reception condition. The communication apparatus further comprises a pattern detection unit configured to detect a characteristic pattern in the first demodulated signal to output a pattern detection signal, and a pitch detection unit configured to detect a pitch of the characteristic pattern based on the pattern detection signal to output a first signal detection signal indicating that the first demodulated signal is one of an in-phase signal and a quadrature signal, or an inverted version of the one of the in-phase signal and the quadrature signal.

Abstract: The invention concerns an optical transmitter and receiver, and provides an improved timing extraction circuit for use in an optical receiver that uses a clock of a frequency equal to one half the data transmission rate, and a duty cycle deviation handling circuit for use in the optical transmitter and receiver. The timing extraction circuit uses a PLL circuit containing a phase comparator circuit for performing a phase comparison between a data signal of bit rate B (bits/s) and a clock signal of B/2 (Hz) at intervals of 2/B (sec), and comprises: a detection circuit for detecting the absence of an output of phase comparison information from the phase comparator circuit by receiving a data signal of a prescribed pattern; and a control circuit for controlling, upon detecting the absence, the phase of the clock signal in order to maintain synchronization.

Abstract: A phase comparison circuit for outputting a phase difference signal indicating a phase difference between a data signal and a clock signal is disclosed. The disclosed phase comparison circuit includes: a detection part for outputting a plurality of signals indicating phases of the data signal according to different decision threshold levels; a phase comparison part for outputting phase difference signals each indicating a phase difference between a signal in the plurality of signals output from the detection part and the clock signal; and a control part for determining whether to output a particular phase difference signal in the phase difference signals by using the whole or a part of the phase deference signals.