Patents by Inventor Naoto Kimura

Naoto Kimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020135050
    Abstract: A semiconductor device comprises a mounting board, a package electrically connected to the mounting board through connection balls attached to the mounting board, a semiconductor chip carried on the package, and bonding wires for electrically connecting connection terminals provided on the semiconductor chip to the connection balls, the semiconductor chip and the connection balls are attached to one surface of a tape, the tape has such a shape that is bent by 180° to make a surface of the tape having the semiconductor chip attached thereon in substantially parallel to a surface of the tape having the connection balls attached thereon with a buffering material intervening therebetween, and the bonding wires and the connection balls are electrically connected to each other with connection wiring formed in the tape.
    Type: Application
    Filed: March 14, 2002
    Publication date: September 26, 2002
    Applicant: NEC CORPORATION
    Inventor: Naoto Kimura
  • Publication number: 20020100977
    Abstract: A downsized semiconductor device comprises a plurality of bonding pads formed on a surface of a semiconductor chip. A plurality of conductive wires are coupled to the bonding pad and extends away from the surface of the semiconductor chip. The surface of the semiconductor chip and the periphery of the plurality of conductive wires are covered with a resin layer. Each of the conductive wires and the resin layer covering the periphery of the conductive wire forms a coaxial body. A plurality of solder balls are mounted on the top end portion of the coaxial bodies and are electrically coupled with the conductive wires. Reinforcement resin portions are provided each of which is attached to an area from an upper end portion of the coaxial body to the solder ball to reinforce the coupling of the solder ball with the coaxial body.
    Type: Application
    Filed: January 28, 2002
    Publication date: August 1, 2002
    Applicant: NEC CORPORATION
    Inventor: Naoto Kimura
  • Publication number: 20020096785
    Abstract: A semiconductor device in which a plurality of semiconductor chips are stacked. The semiconductor device comprises: a lower side semiconductor chip bonded onto a surface of a wiring substrate; an upper side semiconductor chip; and one or more spacers which are bonded onto the surface of the wiring substrate and which support the upper side semiconductor chip over the lower side semiconductor chip and at a location separated from the lower side semiconductor chip. The upper side semiconductor chip and the lower side semiconductor chip are electrically coupled with the wiring substrate, and whole components on the wiring substrate are encapsulated by an encapsulating resin. The size of the upper side semiconductor chip can be larger than that of the lower side semiconductor chip.
    Type: Application
    Filed: January 24, 2002
    Publication date: July 25, 2002
    Applicant: NEC CORPORATION
    Inventor: Naoto Kimura
  • Publication number: 20020053727
    Abstract: The present invention provides a semiconductor device having a substrate on which a plurality of semiconductor chips are stacked, wherein the semiconductor device comprising; a first semiconductor chip mounted on the substrate, a plurality of second semiconductor chips size of which are larger than that of the first semiconductor chip and stacked on the first semiconductor chip with a size-increasing order, a bonding pad formed on the semiconductor chip, a circuit pattern formed on the substrate, a bonding wire for connecting the bonding pad formed on the semiconductor chip and the circuit pattern formed on the substrate, a through hole, formed on the substrate, through which the bonding wire is to be inserted, and further wherein the bonding wire is wired so as to be substantially perpendicularly to a surface of the semiconductor chip.
    Type: Application
    Filed: August 29, 2001
    Publication date: May 9, 2002
    Inventor: Naoto Kimura
  • Publication number: 20020011654
    Abstract: A first semiconductor chip is mounted on a printed circuit board and a second semiconductor chip is mounted on said first semiconductor chip. The second semiconductor chip is displaced in a special direction from the center of the first semiconductor chip. This obviates the need for relay terminals on the side of the first semiconductor chip toward which the second semiconductor chip has been displaced. This allows the first semiconductor chip to be reduced in size by the area that would otherwise be occupied by the relay terminals, and thereby reduces the size of the semiconductor device.
    Type: Application
    Filed: July 19, 2001
    Publication date: January 31, 2002
    Inventor: Naoto Kimura
  • Publication number: 20020011911
    Abstract: A high-frequency choke coil achieves the same low loss across a wide band as a choke coil comprising an external resistor, without using an external resistor. The choke coil comprises a wire-like conductor, wound around a rod-like core; a plurality of individual rod-like cores are joined parallel to their axes with insulators therebetween, forming a rod-like core having a predetermined length; one of the individual rod-like cores has at least (i) a specific dielectric constant at 1 MHz which is more than five times that of the other individual rod-like cores, and/or (ii) a volume resistivity which is less than one-hundredth of that of the other individual rod-like cores.
    Type: Application
    Filed: July 30, 2001
    Publication date: January 31, 2002
    Inventors: Naoto Kimura, Asao Ishikawa
  • Publication number: 20020008311
    Abstract: A semiconductor device has a gap between a semiconductor chip mounted on a mounting plate and a glass epoxy substrate to be attached, and, at the time of resin sealing, molten resin is injected into the gap to form an adhesive layer. Thereby, the adhesive needed conventionally is not needed. In addition, by providing a metal mounting plate having excellent heat conductivity to the rear surface of the semiconductor chip, the high heat radiation effect can be obtained, thereby it can be applied to large-scale array.
    Type: Application
    Filed: July 6, 2001
    Publication date: January 24, 2002
    Inventor: Naoto Kimura
  • Patent number: 6331738
    Abstract: A semiconductor device is provided with a semiconductor chip and a connection lead connected to a pad of the semiconductor chip. The connection lead has a tip part which is bent up to a surface of the semiconductor chip on the opposite side of the pad. The semiconductor device is further provided a resin sealed part covering the semiconductor chip and a solder ball provided on the tip part of the connection lead.
    Type: Grant
    Filed: November 19, 1999
    Date of Patent: December 18, 2001
    Assignee: NEC Corporation
    Inventor: Naoto Kimura
  • Publication number: 20010042916
    Abstract: A semiconductor device is provided with a semiconductor chip. A plurality of electrode pads are arranged in rows running in a first direction on a surface of the semiconductor chip. The semiconductor device is provided with a substrate bonded to the surface, solder balls formed on the substrate, and wires for connecting the solder balls respectively to the corresponding electrode pads. A first slit matching the electrode pads and running in the first direction and a second slit running in a second direction perpendicular to the first direction are provided to the substrate to divide the substrate into at least four regions.
    Type: Application
    Filed: June 21, 2001
    Publication date: November 22, 2001
    Inventor: Naoto Kimura
  • Patent number: 6268652
    Abstract: In a CSP type semiconductor device and a manufacturing method thereof, each pad on a semiconductor chip is connected to an end part of a lead through wire bonding which is mechanicalLy bent to form a bending part, each end part is shifted toward the semiconductor chip, and a mold resin is applied on the above constituents.
    Type: Grant
    Filed: August 31, 1998
    Date of Patent: July 31, 2001
    Assignee: NEC Corporation
    Inventor: Naoto Kimura
  • Patent number: 6239376
    Abstract: A coated fine metallic wire intended for use as a bonding wire in a semiconductor device, includes a fine metallic wire and an insulative layer which contains a pigment or dye which causes the insulative layer to absorb laser light at a high efficiency. The insulative layer is readily removable with a laser light, with no carbonized matter remaining on the fine wire and without damaging the fine wire.
    Type: Grant
    Filed: October 16, 1998
    Date of Patent: May 29, 2001
    Assignee: NEC Corporation
    Inventors: Naoto Kimura, Takahiro Ito
  • Patent number: 6218728
    Abstract: Disclosed is a mold-BGA-type semiconductor device which has: a semiconductor chip which includes insulating resin film formed on at least a part of the surface of the semiconductor chip except a pad; a conductive layer formed in a region on the insulating resin film, the region including at least part corresponding to a position where a solder ball is mounted; a first metal thin wire which is wire-bonded between the pad and the conductive layer; a second metal thin wire which is wire-bonded on the conductive layer; resin part which seals the semiconductor chip, the resin part including a hole to expose part of the second metal thin wire; and a solder ball which is mounted on the hole.
    Type: Grant
    Filed: October 26, 1998
    Date of Patent: April 17, 2001
    Assignee: NEC Corporation
    Inventor: Naoto Kimura
  • Patent number: 6028356
    Abstract: There is provided a plastic-packaged semiconductor integrated circuit including (a) an inner lead having a lead-on-chip (LOC) type structure, (b) a ball grid array (BGA) type terminals for electrically connecting the inner lead to an external circuit, and (c) an outer package made of thermosetting resin for shielding the inner lead therein.
    Type: Grant
    Filed: November 3, 1997
    Date of Patent: February 22, 2000
    Assignee: NEC Corporation
    Inventor: Naoto Kimura
  • Patent number: 6011306
    Abstract: A pad on a semiconductor chip is connected to a solder ball, which communicates with an external circuit, without using a lead, thereby increasing the degree of freedom of bonding, and miniaturizing the semiconductor device. An insulative shaft provided with conductive parts on its surface is attached to the semiconductor chip generally parallel to the surface of the chip. The pad on the chip is connected to the conductove part of the insulator shaft via a bonding wire, and the solder ball is joined to the conductive part.
    Type: Grant
    Filed: September 21, 1998
    Date of Patent: January 4, 2000
    Assignee: NEC Corporation
    Inventor: Naoto Kimura
  • Patent number: 5962918
    Abstract: A semiconductor integrated circuit device has a protective structure between a semiconductor chip and a ball grid array, and the protective structure has a thin polyimide film bonded to the surface of the semiconductor chip and a thick stress relaxation layer covering conductive strips connected between pads on the surface and the ball grid array; when thermal stress is exerted on the ball grid array, the thick stress relaxation layer allows said ball grid array to move so as to take up the thermal stress.
    Type: Grant
    Filed: October 13, 1998
    Date of Patent: October 5, 1999
    Assignee: NEC Corporation
    Inventor: Naoto Kimura
  • Patent number: 5715593
    Abstract: There is provided a plastic-packaged semiconductor integrated circuit including (a) an inner lead having a lead-on-chip (LOC) type structure,(b) a ball grid array (BGA) type terminals for electrically connecting the inner lead to an external circuit, and (c) an outer package made of thermosetting resin for shielding the inner lead therein.
    Type: Grant
    Filed: January 29, 1997
    Date of Patent: February 10, 1998
    Assignee: NEC Corporation
    Inventor: Naoto Kimura
  • Patent number: 5663594
    Abstract: A ball grid type of semiconductor device is provided which includes a semiconductor chip having a plurality of electrode pads. In one preferred embodiment, the semiconductor chip is adhered to a plurality of corresponding planar metal leads via an insulator. The plurality of electrode pads and the plurality of corresponding metal leads are bonded by wires. The semiconductor chip and the plurality of metal leads are sealed together with the wires with a material. A predetermined number of holes passing through the seal to the plurality of metal leads are formed by a laser beam or a drill. Then, solder bails are melted to connect each of the solder balls to a corresponding one of the plurality of metal leads. Finally, the plurality of metal leads are cut at the outer surface of the seal.
    Type: Grant
    Filed: November 15, 1995
    Date of Patent: September 2, 1997
    Assignee: NEC Corporation
    Inventor: Naoto Kimura
  • Patent number: 5168805
    Abstract: A screen printing method comprises an aligning process for fixing a master plate (10) to a fixing frame (20) in aligned relation thereto, an exposure process of exposing a screen printing plate (50) through the master plate (10) fixed to the fixing frame (20), a developing process for developing the thus exposed screen printing plate (50), and a printing process for printing a workpiece (80) by using the thus developed screen printing plate (50). In the aligning process, the positioning pins (22a, 22b, 22c) of the fixing frame (20) abut against the positioning protuberances (62a, 62b, 62c) of a fixing block (61). In the exposure process, the positioning pins (22a, 22b, 22c) of the fixing frame (20) abut against the positioning protuberances (32a, 32b, 32c) of a positioning block (3), while the positioning pins (52a, 52b, 52c) of the printing plate (51) holding the screen printing plate (50) abut against the positioning protuberances (62a, 62b, 62c) of the fixing block (61).
    Type: Grant
    Filed: October 23, 1991
    Date of Patent: December 8, 1992
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Tohru Kasanami, Shigeo Nakatsuji, Mitsuro Hamuro, Naoto Kimura