Abstract: Selective high-energy impurity implantation enables optimization of both core and peripheral field isolation without substantially degrading functionality, self-boosting efficiency or otherwise increasing program disturb, thereby improving device performance and reliability. Embodiments include high-energy impurity implantation, after forming core and peripheral field oxide regions in a semiconductor substrate, into the peripheral field oxide region and selected portions of the core field oxide regions corresponding to select transistor areas, while blocking the implant from the core memory cell channel regions. A channel stop implant is performed through the core field oxide regions after etching a first polysilicon layer. The high-energy impurity implant optimizes peripheral field isolation, without degrading self-boosting efficiency, because it is blocked from entering the memory cell channel region.

Abstract: A method of erasing a memory cell that has a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that contains an initial amount of charge. The method includes applying a first cycle of voltages across the gate and the first region so that the first amount of charge is removed from the charge trapping region. A second amount of charge is written into the charge trapping region and subsequently a second cycle of one or more voltages is applied across the gate and the first region so that the second amount of charge is removed from the charge trapping region, wherein the initial applied voltage of the second cycle of voltages is equal to the final applied voltage of the first cycle of voltages.

Abstract: A method and circuit for sensing multi states of a NAND memory cell by varying source bias, at a constant gate voltage, preferably zero volts, generating a memory cell current in response to the source bias, and sensing the memory cell state.

Abstract: A high voltage transistor exhibiting high gated diode breakdown voltage is formed while avoiding an excessive number of costly masking steps. Embodiments include providing a high gated diode breakdown voltage by masking the high voltage junctions from the conventional field implant, masking the source/drain regions from the conventional threshold adjust implant, providing a thick gate oxide layer, employing a very lightly doped n-type implant in lieu of conventional n+ and LDD implants, and forming contacts to the source and drain regions at a minimum distance from the gate.

Abstract: A method and circuit for sensing multi states of a NAND memory cell by applying reverse bias voltage at a constant gate voltage, preferably zero volts, generating a memory cell current in response to the applied reverse P well bias, and sensing the memory cell state.

Abstract: An intermediate implant step is performed to optimize the performance of the transistors in the peripheral portion of a floating gate type memory integrated circuit. The polysilicon layer (Poly 1) that forms the floating gate in the respective floating gate type memory devices prevents penetration of the optimizing implant into the core region in which the floating gate memory devices are formed. This permits the optimization implant to be performed without the need for an additional mask, thus reducing costs and production time.

Abstract: A high voltage transistor exhibiting high gated diode breakdown voltage, low leakage and low body effect is forced while avoiding an excessive number of costly masking steps. Embodiments include providing a high gated diode breakdown voltage by masking the high voltage junctions from the conventional field implant, masking the source/drain regions from the conventional threshold adjust implant, and employing a very lightly doped n-type implant in lieu of conventional n+ and LDD implants. Appropriate openings are formed in the field implant blocking mask so that the field implant occurs at the edges of the junctions, thus achieving low leakage. The field implant blocking mask is extended over the channel area, thereby producing a transistor with low body effect.

Abstract: This invention describes methods for producing gate oxide regions in periphery regions of semiconductor chips, wherein the gate oxide regions have improved electrical properties. The methods involve the deposition of a barrier layer over the periphery of the semiconductor chip to prevent the introduction of contaminating nitrogen atoms into the periphery during a nitridation step in the core region of the semiconductor chip. By preventing the contamination of the gate areas of the periphery, the gate oxide regions so produced have increased breakdown voltages and increased reliability. This invention describes methods for etching the barrier layers used to protect the periphery from tunnel oxide nitridation. Semiconductor devices made with the methods of this invention have longer expected lifetimes and can be manufactured with higher device density.

Abstract: A NAND flash memory system is programmed with minimal program disturb and pass disturb during self-boosting without resorting to impurity implantation for bit line isolation, to p-well biasing or to bit line biasing techniques. A program voltage is applied to a selected word line in the form of a plurality of short pulses while synchronously applying a pulsed pass voltage to the unselected word lines until the selected cell is programmed. The duration of the pulses and the time between pulses are chosen to minimize the program disturb of unselected cells, especially unselected cells on the selected word line, without causing pass disturb of any cell in the array.

Abstract: According to an aspect of the embodiments, the block decoder control circuits which drive the pass transistors for the word lines for a flash memory array are driven with a control voltage that is regulated to be one enhancement transistor's threshold voltage higher than the highest voltage that is actually driven onto the word lines. According to another aspect of some of the embodiments, the block decoder control circuits are implemented with transistors having a very low threshold voltage. According to yet another aspect of some of the embodiments, a special series connection is used to prevent any leakage current through the block decoder control circuit from the high voltage generating charge pumps which might otherwise result from the use of low threshold voltage transistors. In the special series connection, any leakage current occurs from the supply voltage source rather than from the high voltage generating charge pumps.

Abstract: According to an aspect of the embodiments, the block decoder control circuits which drive the pass transistors for the word lines for a flash memory array are driven with a control voltage that is regulated to be one enhancement transistors threshold voltage higher than the highest voltage that is actually driven onto the word lines. According to another aspect of some of the embodiments, the block decoder control circuits are implemented with transistors having a very low threshold voltage. According to yet another aspect of some of the embodiments, a special series connection is used to prevent any leakage current through the block decoder control circuit from the high voltage generating charge pumps which might otherwise result from the use of low threshold voltage transistors. In the special series connection, any leakage current occurs from the supply voltage source rather than from the high voltage generating charge pumps.