Patents by Inventor Natan Manevich
Natan Manevich has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240154712Abstract: A system for maintaining a Precision Time Protocol (PTP) hardware clock, the system being operative in conjunction with a network device which is external to the system, the system comprising a controller to receive information characterizing a network peer oscillator frequency, wherein the information was extracted from an RX symbol rate, and to adjust the PTP Hardware Clock's frequency responsive to the information characterizing the network peer oscillator frequency.Type: ApplicationFiled: January 18, 2024Publication date: May 9, 2024Inventors: Bar Shapira, Ariel Almog, Dotan David Levi, Natan Manevich, Thomas Kernen, Liron Mula
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Publication number: 20240146431Abstract: In one embodiment, a system includes a network interface controller including a device interface to connect to a processing device and receive a time synchronization marker message from an application running on the processing device, a network interface to send packets over a network, and packet processing circuitry to process the time synchronization marker message for sending via the network interface over the network to a slave clock device, generate a time synchronization follow-up message including a timestamp indicative of when the synchronization marker message egressed the network interface, and process the time synchronization follow-up message for sending via the network interface over the network to the slave clock device.Type: ApplicationFiled: October 26, 2022Publication date: May 2, 2024Inventors: Wojciech Wasko, Dotan David Levi, Avi Urman, Natan Manevich
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Publication number: 20240134731Abstract: A device includes a hardware block to perform a hardware process and internal logic coupled between a processing device, which executes instructions, and the hardware block. The internal logic can one of measure execution time or count clock cycles of at least a portion of the hardware process. The internal logic can further, in response to the measured execution time or the counted clock cycles satisfying a predetermined condition, provide data associated with the one of the execution time measurement or the clock cycles count to the processing device, the data being statistically indicative of a latency of data packets sent by the hardware process over a total time the hardware process executes.Type: ApplicationFiled: December 5, 2022Publication date: April 25, 2024Inventors: Natan Manevich, Dotan David Levi, Shay Aisman, Ariel Almog, Ran Avraham Koren
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Publication number: 20240097876Abstract: A communication system includes at least one send queue, containing send queue entries pointing to packets to be transmitted over a network by packet sending circuitry. A clock work queue contains clock queue entries to synchronize sending times of the packets pointed to by the send queue entries. At least one arming queue contains arming queue entries to arm the clock work queue at selected time intervals.Type: ApplicationFiled: November 30, 2023Publication date: March 21, 2024Inventors: Dotan David Levi, Ariel Shahar, Shahaf Shuler, Ariel Almog, Eitan Hirshberg, Natan Manevich
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Publication number: 20240089077Abstract: A network interface device includes a local register and packet processing circuitry coupled to the local register. The packet processing circuitry is to: capture a network packet transmitted by a software application running on an integrated computing system; capture, at time of transmission of the network packet, a value of a physical clock as a receive timestamp for subscriber entities that are running on the integrated computing system; store the receive timestamp in the local register; associate the receive timestamp from the local register with a first packet copy of the network packet; insert the first packet copy to a first receive pipeline of a first subscriber entity; associate the receive timestamp from the local register with a second packet copy of the network packet; and insert the second packet copy to a second receive pipeline of a second subscriber entity.Type: ApplicationFiled: September 12, 2022Publication date: March 14, 2024Inventors: Wojciech Wasko, Dotan David Levi, Natan Manevich, Maciek Machnikowski
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Patent number: 11917045Abstract: In one embodiment, a communication system includes network devices, each comprising a network interface to receive at least one data stream, a given network device being configured to recover a remote clock from the at least one data stream received by the given network device, a frequency synthesizer to generate a clock signal and output the clock signal to each of the network devices, wherein the given network device is configured to find a clock frequency differential between the clock signal and the recovered remote clock, and provide a control signal to the frequency synthesizer responsively to the clock frequency differential, the control signal causes the frequency synthesizer to adjust the clock signal so as to iteratively reduce an absolute value of the clock frequency differential between the clock signal and the recovered remote clock.Type: GrantFiled: July 24, 2022Date of Patent: February 27, 2024Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Dotan David Levi, Arnon Sattinger, Natan Manevich, Wojciech Wasko, Ariel Almog, Bar Or Shapira
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Patent number: 11907754Abstract: In one embodiment, a system includes a memory, a processing device including a device processor; and a device clock, and a peripheral device including an interface to share data with the processing device, a hardware clock, and processing circuitry to write respective interrupt signaling messages to the memory responsively to respective hardware clock values of the hardware clock, and wherein the device processor is configured, responsively to the respective interrupt signaling messages being written to the memory, to perform a time-dependent action.Type: GrantFiled: December 14, 2021Date of Patent: February 20, 2024Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Wojciech Wasko, Dotan David Levi, Liron Mula, Natan Manevich
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Publication number: 20240031121Abstract: In one embodiment, a communication system includes network devices, each comprising a network interface to receive at least one data stream, a given network device being configured to recover a remote clock from the at least one data stream received by the given network device, a frequency synthesizer to generate a clock signal and output the clock signal to each of the network devices, wherein the given network device is configured to find a clock frequency differential between the clock signal and the recovered remote clock, and provide a control signal to the frequency synthesizer responsively to the clock frequency differential, the control signal causes the frequency synthesizer to adjust the clock signal so as to iteratively reduce an absolute value of the clock frequency differential between the clock signal and the recovered remote clock.Type: ApplicationFiled: July 24, 2022Publication date: January 25, 2024Inventors: Dotan David Levi, Arnon Sattinger, Natan Manevich, Wojciech Wasko, Ariel Almog, Bar Or Shapira
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Publication number: 20240031124Abstract: In one embodiment, a clock syntonization system includes a first compute node including a first physical hardware clock to operate at a first clock frequency, a second compute node, and an interconnect data bus to transfer data from the first compute node at a data rate indicative of the first clock frequency of the first physical hardware clock, and wherein the second compute node includes clock synchronization circuitry to derive a second clock frequency from the data rate of the transferred data, and provide a clock signal at the derived second clock frequency.Type: ApplicationFiled: July 20, 2022Publication date: January 25, 2024Inventors: Dotan David Levi, Wojciech Wasko, Natan Manevich
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Patent number: 11876885Abstract: A timing system including timing circuitry which includes an arming queue, a clock work queue, and a clock completion queue. At least the clock work queue is to provide timing information, and the arming queue is to arm the clock work queue. Related apparatus and methods are also provided.Type: GrantFiled: June 1, 2021Date of Patent: January 16, 2024Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Dotan David Levi, Ariel Shahar, Shahaf Shuler, Ariel Almog, Eitan Hirshberg, Natan Manevich
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Patent number: 11853116Abstract: In one embodiment, a device includes a hardware clock to maintain a clock value, a hardware counter to maintain an estimation of a dynamic error bound of the clock value, and a clock controller to intermittently discipline the hardware clock responsively to a remote clock, advance the hardware counter at a rate responsively to a clock drift, and adjust the hardware counter responsively to the hardware clock being disciplined.Type: GrantFiled: January 24, 2022Date of Patent: December 26, 2023Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Dotan David Levi, Wojciech Wasko, Eitan Zahavi, Natan Manevich, Bar Shapira
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Patent number: 11835999Abstract: A system is disclosed that includes two or more network elements, each comprising a Precision Time Protocol (PTP) Hardware Clock (PHC) that is adjustable based, at least in part, on physical layer frequency information.Type: GrantFiled: January 18, 2022Date of Patent: December 5, 2023Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Bar Shapira, Ariel Almog, Dotan David Levi, Natan Manevich, Thomas Kernen
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Publication number: 20230370305Abstract: In one embodiment, a synchronized communication system includes a plurality of network devices, and clock connections to connect the network devices in a closed loop configuration, wherein the network devices are configured to distribute among the network devices a reference clock time from any selected one of the network devices.Type: ApplicationFiled: August 11, 2022Publication date: November 16, 2023Inventors: Natan Manevich, Dotan David Levi, Wojciech Wasko, Ariel Almog, Bar Shapira
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Publication number: 20230367358Abstract: In one embodiment, a synchronized communication system includes a first network device and a second network device, wherein the first network device includes a first physical hardware clock, and is configured to recover a reference clock time from packets received from a remote clock, find a clock differential between a clock time output by the first physical hardware clock and the recovered reference clock time, provide a control signal to the second network device responsively to the clock differential, and the second network device includes a second physical hardware clock, and is configured to adjust a clock time output by the second physical hardware clock responsively to the control signal.Type: ApplicationFiled: July 19, 2022Publication date: November 16, 2023Inventors: Natan Manevich, Dotan David Levi, Wojciech Wasko, Ariel Almog, Bar Shapira
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Publication number: 20230362097Abstract: Aspects of the present disclosure are directed to systems, methods, and computer readable media for dynamic data transfer rate control. One method includes alternating a network device between a plurality of supported data transfer rates that are supported by the network device to achieve an unsupported data transfer rate that is not supported by the network device. Another method includes adding one or more dummy work descriptors to a data stream, and transmitting the data stream including the one or more dummy work descriptors at a supported data transfer rate that is supported by a network device to achieve an effective unsupported data transfer rate that is not supported by the network device.Type: ApplicationFiled: November 18, 2022Publication date: November 9, 2023Inventors: Natan Manevich, Dotan David Levi, Alex Vaynman, Roee Moyal, Alex Rosenbaum, Stanislav Raitsyn, Yuval Atias
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Publication number: 20230362084Abstract: A system includes a device configured to execute workloads coupled to a processing device. The processing device is to receive a request to execute one or more workloads, the request comprising two or more numbers corresponding to a rational value associated with a rate to execute the one or more workloads. The processing device is further to determine the rate to execute the one or more workloads responsive to receiving the two or more numbers corresponding to the rational values. The processing device is to execute the one or more workloads at the determined rate.Type: ApplicationFiled: February 7, 2023Publication date: November 9, 2023Inventors: Natan Manevich, Dotan David Levi, Alex Vainman, Roee Moyal
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Publication number: 20230361900Abstract: A system includes a device coupled to a processing device. The processing device is to receive a timing signal associated with a synchronized time. The processing device is further to synchronize a rate limiter of the device to the synchronized time responsive to receiving the timing signal, wherein the rate limiter is configured to schedule one or more workloads at a respective rate. The processing device is to receive a request to execute the one or more workloads, the request comprising a rate to execute each workload of the one or more workloads. The processing device is to execute the one or more workloads at the respective rate upon synchronizing the rate limiter.Type: ApplicationFiled: February 8, 2023Publication date: November 9, 2023Inventors: Dotan David Levi, Liron Mula, Natan Manevich
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Publication number: 20230362096Abstract: A system includes a device coupled to a processing device. The processing device is to receive a request to execute a plurality of workloads, the request comprising a rate to execute each workload of the plurality of workloads and a parameter value indicating an execution offset. The processing device is further to determine a sequence for executing the plurality of workloads based on receiving the rate and the parameter value, where the sequence is to execute each workload at the respective rate and each workload of the plurality of workloads is executed at a different time based on the parameter value. The processing device is to execute the plurality of workloads in accordance with the sequence upon determining the sequence to execute the plurality of workloads.Type: ApplicationFiled: February 7, 2023Publication date: November 9, 2023Inventors: Natan Manevich, Dotan David Levi, Roee Moyal
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Patent number: 11757614Abstract: In one embodiment, a processing apparatus includes processing circuitry to process an event, a timestamping unit to generate a timestamp for the event, at least one register to store at least one parameter describing a hardware state of the processing circuitry, and timestamp correction processing circuitry to compute a time value as a correction to the generated timestamp responsively to the at least one parameter.Type: GrantFiled: May 10, 2021Date of Patent: September 12, 2023Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Dotan David Levi, Wojciech Wasko, Natan Manevich, Teferet Geula, Amit Mandelbaum, Ariel Almog
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Publication number: 20230269684Abstract: A network adapter comprises an output that couples to a central processing unit (CPU) of a network device, a first clock coupled to the output and configured to be synchronized with a second clock that is external to the CPU and the network adapter, and circuitry coupled to the first clock. The circuitry is configured to generate, using the synchronized first clock, a tick at a time offset from a timeslot of a radio schedule for a radio unit and send the tick to the output.Type: ApplicationFiled: February 18, 2022Publication date: August 24, 2023Inventors: Wojciech Wasko, Dotan David Levi, Natan Manevich, Timothy James Martin