Patents by Inventor Naushad K. Variam
Naushad K. Variam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11948832Abstract: A semiconductor manufacturing process and semiconductor device having an airgap to isolate bottom implant portions of a substrate from upper source and drain device structure to reduce bottom current leakage and parasitic capacitance with an improved scalability on n-to-p spacing scaling. The disclosed device can be implanted to fabricate nanosheet FET and other such semiconductor device. The airgap is formed by etching into the substrate, below a trench in a vertical and horizontal direction. The trench is then filled with dielectric and upper device structure formed on either side of the dielectric filler trench.Type: GrantFiled: September 21, 2021Date of Patent: April 2, 2024Assignee: Applied Materials, Inc.Inventors: Yan Zhang, Johannes M. van Meer, Naushad K. Variam
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Patent number: 11942361Abstract: Disclosed are approaches for forming semiconductor device cavities using directional dielectric deposition. One method may include providing a plurality of semiconductor structures and a plurality of trenches of a semiconductor device, and forming a dielectric atop the plurality of semiconductor structures by delivering a dielectric material at a non-zero angle of inclination relative to a normal extending perpendicular from a top surface of the plurality of semiconductor structures. The dielectric may be further formed by delivering the dielectric material at a second non-zero angle of inclination relative to the normal extending perpendicular from the top surface of the plurality of semiconductor structures.Type: GrantFiled: June 15, 2021Date of Patent: March 26, 2024Assignee: Applied Materials, Inc.Inventors: Armin Saeedi Vahdat, Tristan Y. Ma, Johannes M. van Meer, John Hautala, Naushad K. Variam
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Publication number: 20230369453Abstract: A method for forming a nanosheet device. The method may include providing a heterostructure device stack above a semiconductor substrate. The method may include patterning the heterostructure device stack to define a dummy gate region, and before forming a source drain recess adjacent the dummy gate region, selectively removing a first set of sacrificial layers of the heterostructure device stack within the dummy gate region.Type: ApplicationFiled: May 13, 2022Publication date: November 16, 2023Applicant: Applied Materials, Inc.Inventors: Yan Zhang, Johannes M. van Meer, Sankuei Lin, Baonian Guo, Naushad K. Variam
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Patent number: 11778832Abstract: Disclosed are approaches for 3D NAND structure fabrication. One method may include providing a stack of layers comprising a first and second plurality of layers, and forming a plurality of trenches in the stack of layers, wherein each of the trenches includes a tiered sidewall. A first trench may be formed to a first depth, and a second trench may be formed to a second depth, which is greater than the first depth. The method may further include forming a liner within the trenches, wherein the liner is deposited at a non-zero angle of inclination relative to a normal extending perpendicular from the top surface of the stack of layers. The liner may have a first thickness along the tiered sidewall of the first trench and a second thickness along the tiered sidewall of the second trench, wherein the first thickness is greater than the second thickness.Type: GrantFiled: May 3, 2021Date of Patent: October 3, 2023Assignee: Applied Materials, Inc.Inventors: Armin Saeedi Vahdat, Tristan Y. Ma, Johannes M. van Meer, John Hautala, Naushad K. Variam
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Publication number: 20230187210Abstract: Approaches herein provide devices and methods for forming optimized gate-all-around transistors. One method may include forming a well by directing a first ion species into a substrate of a device, forming a plurality of alternating first and second layers over the well, and forming a dummy gate and a spacer over the plurality of alternating first and second layers. The method may further include removing a portion of the plurality of alternating first and second layers to expose an upper surface of the well, forming a punch through stopper in the well by directing a second ion species into the exposed upper surface of the well, etching the plurality of nanosheets to laterally recess the second layers relative to the first layers, and forming an inner spacer along the first and second layers.Type: ApplicationFiled: December 10, 2021Publication date: June 15, 2023Applicant: Applied Materials, Inc.Inventors: Yan Zhang, Johannes M. van Meer, Naushad K. Variam
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Publication number: 20230089482Abstract: A semiconductor manufacturing process and semiconductor device having an airgap to isolate bottom implant portions of a substrate from upper source and drain device structure to reduce bottom current leakage and parasitic capacitance with an improved scalability on n-to-p spacing scaling. The disclosed device can be implanted to fabricate nanosheet FET and other such semiconductor device. The airgap is formed by etching into the substrate, below a trench in a vertical and horizontal direction. The trench is then filled with dielectric and upper device structure formed on either side of the dielectric filler trench.Type: ApplicationFiled: September 21, 2021Publication date: March 23, 2023Applicant: Applied Materials, Inc.Inventors: Yan Zhang, Johannes M. van Meer, Naushad K. Variam
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Publication number: 20220399225Abstract: Disclosed are approaches for forming semiconductor device cavities using directional dielectric deposition. One method may include providing a plurality of semiconductor structures and a plurality of trenches of a semiconductor device, and forming a dielectric atop the plurality of semiconductor structures by delivering a dielectric material at a non-zero angle of inclination relative to a normal extending perpendicular from a top surface of the plurality of semiconductor structures. The dielectric may be further formed by delivering the dielectric material at a second non-zero angle of inclination relative to the normal extending perpendicular from the top surface of the plurality of semiconductor structures.Type: ApplicationFiled: June 15, 2021Publication date: December 15, 2022Applicant: Applied Materials, Inc.Inventors: Armin Saeedi Vahdat, Tristan Y. Ma, Johannes M. van Meer, John Hautala, Naushad K. Variam
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Publication number: 20220352182Abstract: Disclosed are approaches for 3D NAND structure fabrication. One method may include providing a stack of layers comprising a first and second plurality of layers, and forming a plurality of trenches in the stack of layers, wherein each of the trenches includes a tiered sidewall. A first trench may be formed to a first depth, and a second trench may be formed to a second depth, which is greater than the first depth. The method may further include forming a liner within the trenches, wherein the liner is deposited at a non-zero angle of inclination relative to a normal extending perpendicular from the top surface of the stack of layers. The liner may have a first thickness along the tiered sidewall of the first trench and a second thickness along the tiered sidewall of the second trench, wherein the first thickness is greater than the second thickness.Type: ApplicationFiled: May 3, 2021Publication date: November 3, 2022Applicant: Applied Materials, Inc.Inventors: Armin Saeedi Vahdat, Tristan Y. Ma, Johannes M. van Meer, John Hautala, Naushad K. Variam
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Patent number: 11217491Abstract: Methods herein may include forming a gate dielectric within a set of trenches in a stack of layers. A first work function (WF) metal may be formed atop the gate dielectric, and a capping layer may be formed over the first WF metal using an angled ion implant deposition, the capping layer extending across the trenches.Type: GrantFiled: July 18, 2019Date of Patent: January 4, 2022Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Min Gyu Sung, Naushad K. Variam, Sony Varghese, Johannes Van Meer, Jae Young Lee
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Publication number: 20210119022Abstract: Methods for forming semiconductor devices herein may include providing a metal gate, an interlayer dielectric (ILD), and an etch stop layer over a plurality of fins, wherein the ILD is formed atop the etch stop layer, and wherein the plurality of fins includes a source/drain (S/D) epitaxial region. The method may further include removing the etch stop layer from atop the S/D epitaxial region, and performing, through an opening in the ILD, an ion implant and a dopant ion implant to the S/D epitaxial region. In some embodiments, the method may further include thermally treating the semiconductor device to activate ions of the ion implant or ions of the dopant ion implant in the S/D epitaxial region to form an ultra-shallow junction.Type: ApplicationFiled: October 22, 2019Publication date: April 22, 2021Applicant: APPLIED Materials, Inc.Inventors: Jae Young Lee, Johannes M. Van Meer, Naushad K. Variam
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Patent number: 10971403Abstract: A method for forming a semiconductor device. The method may include providing a transistor structure, where the transistor structure includes a fin array, the fin array including a plurality of semiconductor fins, disposed on a substrate. A liner may be disposed on the plurality of semiconductor fins. The method may include directing first angled ions to the fin array, wherein the liner is removed in an upper portion of the plurality of semiconductor fins, and wherein the liner remains in a lower portion of the at least one of the plurality of semiconductor fins, and wherein the upper portion comprises an active fin region to form a transistor device.Type: GrantFiled: December 13, 2019Date of Patent: April 6, 2021Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Min Gyu Sung, Naushad K. Variam, Sony Varghese, Johannes Van Meer, Jae Young Lee
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Publication number: 20210050349Abstract: The present disclosure is directed to structures and processing for three-dimensional transistor devices. In some approaches, a method may include providing a plurality of fin structures formed from a substrate, the plurality of fin structures disposed subjacent to a hard mask layer, and directing angled ions at the plurality of fin structures. The angled ions may form a non-zero angle of incidence with respect to a perpendicular to a plane of the substrate, wherein the angled ions etch the plurality of fin structures to form a stack of isolated nanowires within the plurality of fin structures. The method may further include removing the hard mask layer, and forming a stopping layer over the stack of isolated nanowires.Type: ApplicationFiled: August 16, 2019Publication date: February 18, 2021Applicant: APPLIED Materials, Inc.Inventors: ANTHONY RENAU, MIN GYU SUNG, SONY VARGHESE, MORGAN EVANS, NAUSHAD K. VARIAM, TASSIE ANDERSEN
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Patent number: 10903211Abstract: The present disclosure is directed to structures and processing for three-dimensional transistor devices. In some approaches, a method may include providing a plurality of fin structures formed from a substrate, the plurality of fin structures disposed subjacent to a hard mask layer, and directing angled ions at the plurality of fin structures. The angled ions may form a non-zero angle of incidence with respect to a perpendicular to a plane of the substrate, wherein the angled ions etch the plurality of fin structures to form a stack of isolated nanowires within the plurality of fin structures. The method may further include removing the hard mask layer, and forming a stopping layer over the stack of isolated nanowires.Type: GrantFiled: August 16, 2019Date of Patent: January 26, 2021Assignee: Applied Materials, Inc.Inventors: Anthony Renau, Min Gyu Sung, Sony Varghese, Morgan Evans, Naushad K. Variam, Tassie Andersen
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Patent number: 10720357Abstract: A method of forming a semiconductor device. The method may include providing a device structure, where the device structure comprises a masked portion and a cut portion. The masked portion may comprise a mask covering at least one semiconductor fin of a fin array, and the cut portion may comprise a trench, where the trench exposes a semiconductor fin region of the fin array. The method may further include providing an exposure of the trench to oxidizing ions, the oxidizing ions to transform a semiconductor material into an oxide.Type: GrantFiled: March 1, 2018Date of Patent: July 21, 2020Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Min Gyu Sung, Naushad K Variam, Sony Varghese, Johannes Van Meer, Jae Young Lee, Jun Lee
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Patent number: 10692775Abstract: Disclosed are methods of forming a semiconductor device, such as a finFET device. One non-limiting method may include providing a semiconductor device including a substrate and a plurality of fins extending from the substrate, and forming a source trench isolation (STI) material over the semiconductor device. The method may further include recessing the STI material to reveal an upper portion of the plurality of fins, implanting the semiconductor device, and forming a capping layer over the plurality of fins and the STI material. The method may further include removing a first fin section of the plurality of fins and a first portion of the capping layer, wherein a second fin section of the plurality of fins remains following removal of the first fin section.Type: GrantFiled: November 9, 2018Date of Patent: June 23, 2020Assignee: Applied Materials, Inc.Inventors: Min Gyu Sung, Jae Young Lee, Johannes Van Meer, Sony Varghese, Naushad K. Variam
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Patent number: 10686033Abstract: Disclosed are methods of forming a semiconductor device, such as a finFET device. One non-limiting method may include providing a semiconductor device including a substrate and a plurality of fins extending from the substrate, and forming a source trench isolation (STI) material over the semiconductor device. The method may further include performing a fin cut by removing a first fin section of the plurality of fins and a first portion of the STI material, and forming a second STI material over a second fin section of the plurality of fins, wherein the second fin section is left remaining following removal of the first fin section. The method may further include recessing the STI material and the second STI material, forming a spin-on-carbon (SOC) layer over the semiconductor device, and implanting the STI material and the second STI material through the SOC layer.Type: GrantFiled: November 9, 2018Date of Patent: June 16, 2020Assignee: Applied Materials, Inc.Inventors: Min Gyu Sung, Jae Young Lee, Johannes Van Meer, Sony Varghese, Naushad K. Variam
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Publication number: 20200152735Abstract: Disclosed are methods of forming a semiconductor device, such as a finFET device. One non-limiting method may include providing a semiconductor device including a substrate and a plurality of fins extending from the substrate, and forming a source trench isolation (STI) material over the semiconductor device. The method may further include performing a fin cut by removing a first fin section of the plurality of fins and a first portion of the STI material, and forming a second STI material over a second fin section of the plurality of fins, wherein the second fin section is left remaining following removal of the first fin section. The method may further include recessing the STI material and the second STI material, forming a spin-on-carbon (SOC) layer over the semiconductor device, and implanting the STI material and the second STI material through the SOC layer.Type: ApplicationFiled: November 9, 2018Publication date: May 14, 2020Applicant: APPLIED Materials, Inc.Inventors: Min Gyu Sung, Jae Young Lee, Johannes Van Meer, Sony Varghese, Naushad K. Variam
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Publication number: 20200152519Abstract: Disclosed are methods of forming a semiconductor device, such as a finFET device. One non-limiting method may include providing a semiconductor device including a substrate and a plurality of fins extending from the substrate, and forming a source trench isolation (STI) material over the semiconductor device. The method may further include recessing the STI material to reveal an upper portion of the plurality of fins, implanting the semiconductor device, and forming a capping layer over the plurality of fins and the STI material. The method may further include removing a first fin section of the plurality of fins and a first portion of the capping layer, wherein a second fin section of the plurality of fins remains following removal of the first fin section.Type: ApplicationFiled: November 9, 2018Publication date: May 14, 2020Applicant: APPLIED Materials, Inc.Inventors: Min Gyu Sung, Jae Young Lee, Johannes Van Meer, Sony Varghese, Naushad K. Variam
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Publication number: 20200135573Abstract: A method for forming a semiconductor device. The method may include providing a transistor structure, where the transistor structure includes a fin array, the fin array including a plurality of semiconductor fins, disposed on a substrate. A liner may be disposed on the plurality of semiconductor fins. The method may include directing first angled ions to the fin array, wherein the liner is removed in an upper portion of the plurality of semiconductor fins, and wherein the liner remains in a lower portion of the at least one of the plurality of semiconductor fins, and wherein the upper portion comprises an active fin region to form a transistor device.Type: ApplicationFiled: December 13, 2019Publication date: April 30, 2020Applicant: Varian Semiconductor Equipment Associates, Inc.Inventors: Min Gyu Sung, Naushad K. Variam, Sony Varghese, Johannes Van Meer, Jae Young Lee
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Patent number: 10510610Abstract: A method for forming a semiconductor device. The method may include providing a transistor structure, where the transistor structure includes a fin array, the fin array including a plurality of semiconductor fins, disposed on a substrate. A liner may be disposed on the plurality of semiconductor fins. The method may include directing first angled ions to the fin array, wherein the liner is removed in an upper portion of the plurality of semiconductor fins, and wherein the liner remains in a lower portion of the at least one of the plurality of semiconductor fins, and wherein the upper portion comprises an active fin region to form a transistor device.Type: GrantFiled: March 28, 2018Date of Patent: December 17, 2019Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: Min Gyu Sung, Naushad K. Variam, Sony Varghese, Johannes Van Meer, Jae Young Lee