Patents by Inventor Naushad K. Variam

Naushad K. Variam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190341315
    Abstract: Methods herein may include forming a gate dielectric within a set of trenches in a stack of layers. A first work function (WF) metal may be formed atop the gate dielectric, and a capping layer may be formed over the first WF metal using an angled ion implant deposition, the capping layer extending across the trenches.
    Type: Application
    Filed: July 18, 2019
    Publication date: November 7, 2019
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Min Gyu Sung, Naushad K. Variam, Sony Varghese, Johannes Van Meer, Jae Young Lee
  • Publication number: 20190304841
    Abstract: A method for forming a semiconductor device. The method may include providing a transistor structure, where the transistor structure includes a fin array, the fin array including a plurality of semiconductor fins, disposed on a substrate. A liner may be disposed on the plurality of semiconductor fins. The method may include directing first angled ions to the fin array, wherein the liner is removed in an upper portion of the plurality of semiconductor fins, and wherein the liner remains in a lower portion of the at least one of the plurality of semiconductor fins, and wherein the upper portion comprises an active fin region to form a transistor device.
    Type: Application
    Filed: March 28, 2018
    Publication date: October 3, 2019
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Min Gyu Sung, Naushad K. Variam, Sony Varghese, Johannes Van Meer, Jae Young Lee
  • Publication number: 20190273011
    Abstract: A method of forming a semiconductor device. The method may include providing a device structure, where the device structure comprises a masked portion and a cut portion. The masked portion may comprise a mask covering at least one semiconductor fin of a fin array, and the cut portion may comprise a trench, where the trench exposes a semiconductor fin region of the fin array. The method may further include providing an exposure of the trench to oxidizing ions, the oxidizing ions to transform a semiconductor material into an oxide.
    Type: Application
    Filed: March 1, 2018
    Publication date: September 5, 2019
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Min Gyu Sung, Naushad K. Variam, Sony Varghese, Johannes Van Meer, Jae Young Lee, Jun Lee
  • Patent number: 10403552
    Abstract: Methods herein may include forming trenches in a stack of layers atop a substrate, and forming a gate dielectric within the trenches. Methods may further include forming a first work function (WF) metal atop the gate dielectric, and forming a capping layer over the first WF metal using an angled ion implant deposition, the capping layer extending across the trenches. The first WF metal may be removed from just a first trench of the trenches, and a second WF metal is then formed over the stack of layers, wherein the second WF metal is formed atop the gate dielectric within the first trench. An angled ion etch may then be performed to recess the gate dielectric and the second WF metal within the first trench, and to recess the gate dielectric and the first WF metal within a second trench. A gate metal may then be formed within the trenches.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: September 3, 2019
    Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Min Gyu Sung, Naushad K. Variam, Sony Varghese, Johannes Van Meer, Jae Young Lee
  • Patent number: 9337314
    Abstract: A method to selectively process a three dimensional device, comprising providing a substrate having a first surface that extends horizontally, the substrate comprising a structure containing a second surface that extends vertically from the first surface; providing a film on the substrate, the film comprising carbon species; and etching a selected portion of the film by exposing the selected portion of the film to an etchant containing hydrogen species, where the etchant excludes oxygen species and fluorine species.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: May 10, 2016
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Nilay A. Pradhan, Benjamin Colombeau, Naushad K. Variam, Mandar B. Pandit, Christopher Dennis Bencher, Adam Brand
  • Publication number: 20140162414
    Abstract: A method to selectively process a three dimensional device, comprising providing a substrate having a first surface that extends horizontally, the substrate comprising a structure containing a second surface that extends vertically from the first surface; providing a film on the substrate, the film comprising carbon species; and etching a selected portion of the film by exposing the selected portion of the film to an etchant containing hydrogen species, where the etchant excludes oxygen species and fluorine species.
    Type: Application
    Filed: December 11, 2013
    Publication date: June 12, 2014
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Nilay A. Pradhan, Benjamin Colombeau, Naushad K. Variam, Mandar B. Pandit, Christopher Dennis Bencher, Adam Brand
  • Patent number: 7378335
    Abstract: A method for fabricating a semiconductor-based device includes providing a substrate including a semiconductor layer, forming a gate dielectric layer on the semiconductor layer, forming a plasma including deuterium, plasma implanting deuterium from the plasma into the substrate, and annealing the substrate to promote passivation of the interface between the dielectric layer and the semiconductor layer.
    Type: Grant
    Filed: November 29, 2005
    Date of Patent: May 27, 2008
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Steven R. Walther, Ukyo Jeong, Sandeep Mehta, Naushad K. Variam
  • Patent number: 7326937
    Abstract: Plasma ion implantation apparatus includes a process chamber, a platen located in the process chamber for supporting a substrate, a dopant source including a solid dopant element and a vaporizer to vaporize dopant material from the solid dopant element, a plasma source to produce a plasma containing ions of the dopant material, and an implant pulse source to apply implant pulses to the platen for accelerating the ions of the dopant material from the plasma into the substrate.
    Type: Grant
    Filed: March 9, 2005
    Date of Patent: February 5, 2008
    Assignee: Verian Semiconductor Equipment Associates, Inc.
    Inventors: Sandeep Mehta, Steven R. Walther, Naushad K. Variam