Patents by Inventor Navakanta Bhat
Navakanta Bhat has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170241945Abstract: An electrochemically active device is provided for collecting and retaining a blood sample with at least a two-electrode member connected to conductive tracks. A receptor with an integral receptor-membrane arranged on the two-electrode member, to receive non-electrochemically active heamoglobin bioanalyte and its complexes from red blood cells (RBC) of said blood sample, through a lysing agent and convert the non-electrochemically active heamoglobin bioanalyte and its complexes, into an electrochemically active bioanalyte and its electrochemically active complexes. The present invention also provides a point-of-care biosensor incorporated with the device of the present invention and method of measuring for the detection and quantitative measurement of concentrations of haemoglobin (Hb), glycated haemoglobin (GHb), methaemoglobin (MetHb) and myoglobin, in reduced volumes of blood samples, by determining redox current values in the reduced volumes of blood samples.Type: ApplicationFiled: September 7, 2015Publication date: August 24, 2017Inventors: Vinay Kumar, Navakanta Bhat
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Patent number: 9741656Abstract: The present invention provides a high-frequency integrated device, comprising a substrate including at least an on-chip active and passive member and a ferrite layer bonded to the substrate through an interfacial bridge and substantially wrapping plurality of surfaces of said at least on-chip active and passive members. The present invention also provides a system incorporating the high-frequency integrated device of the present invention. The present invention further provides a process for the preparation of the high-frequency integrated device.Type: GrantFiled: October 30, 2013Date of Patent: August 22, 2017Assignee: INDIAN INSTITUTE OF SCIENCEInventors: Ranajit Sai, Srinivasarao Ajjampur Shivshankar, Navakanta Bhat, Vinoy Kalarickaparambil Joseph
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Patent number: 9297671Abstract: A device and method for area sensing and actuation comprises highly scalable sensing and actuation network that can control a high density of sensing and actuation elements over a physical area. The device comprises a matrix of CMOS sensing chips that each comprise a plurality of sensing electrodes arranged in a matrix of columns and rows along horizontal wires and vertical wires. The vertical wires carry an activation signal to activate a column of sensing electrodes, and the vertical wires carry sensing and actuation signals between the column of sensing electrodes and a processing chip. The signals may be amplified by CMOS sensing chips between the source and destination of the signals. In this way, signals may be received from and sent to a dense matrix of sensing electrodes spanning a large geographic area with little or no degradation.Type: GrantFiled: September 1, 2015Date of Patent: March 29, 2016Assignee: INDIAN INSTITUTE OF SCIENCEInventors: Bharadwaj Amrutur, Navakanta Bhat
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Publication number: 20150369634Abstract: A device and method for area sensing and actuation comprises highly scalable sensing and actuation network that can control a high density of sensing and actuation elements over a physical area. The device comprises a matrix of CMOS sensing chips that each comprise a plurality of sensing electrodes arranged in a matrix of columns and rows along horizontal wires and vertical wires. The vertical wires carry an activation signal to activate a column of sensing electrodes, and the vertical wires carry sensing and actuation signals between the column of sensing electrodes and a processing chip. The signals may be amplified by CMOS sensing chips between the source and destination of the signals. In this way, signals may be received from and sent to a dense matrix of sensing electrodes spanning a large geographic area with little or no degradation.Type: ApplicationFiled: September 1, 2015Publication date: December 24, 2015Inventors: BHARADWAJ AMRUTUR, NAVAKANTA BHAT
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Patent number: 9158408Abstract: A device and method for area sensing and actuation comprises highly scalable sensing and actuation network that can control a high density of sensing and actuation elements over a physical area. The device comprises a matrix of CMOS sensing chips that each comprise a plurality of sensing electrodes arranged in a matrix of columns and rows along horizontal wires and vertical wires. The vertical wires carry an activation signal to activate a column of sensing electrodes, and the vertical wires carry sensing and actuation signals between the column of sensing electrodes and a processing chip. The signals may be amplified by CMOS sensing chips between the source and destination of the signals. In this way, signals may be received from and sent to a dense matrix of sensing electrodes spanning a large geographic area with little or no degradation.Type: GrantFiled: August 26, 2010Date of Patent: October 13, 2015Assignee: Indian Institute of ScienceInventors: Bharadwaj Amrutur, Navakanta Bhat
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Publication number: 20150287658Abstract: The present invention provides a high-frequency integrated device, comprising a substrate including at least an on-chip active and passive member and a ferrite layer bonded to the substrate through an interfacial bridge and substantially wrapping plurality of surfaces of said at least on-chip active and passive members. The present invention also provides a system incorporating the high-frequency integrated device of the present invention. The present invention further provides a process for the preparation of the high-frequency integrated device.Type: ApplicationFiled: October 30, 2013Publication date: October 8, 2015Applicant: INDIAN INSTITUTE OF SCIENCEInventors: Ranajit Sai, Srinivasarao Ajjampur Shivshankar, Navakanta Bhat, Vinoy Kalarickaparambil Joseph
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Patent number: 8737547Abstract: An adaptive digital baseband receiver is described in which operating parameters of the receiver, such as bit-widths and operating frequencies, are determined that achieve a target bit-error-ratio (BER) as a function of received signal-to-noise ratio (SNR) and interference levels in a wireless channel and enable the receiver to consume a minimum amount of power. Over consumption of power may be avoided due to a functional relationship between optimal resolution and input signal conditions. In exemplary embodiments, the adaptive digital receiver is provided that adjusts bit-widths and operating frequency at power efficient levels while meeting a target BER. Simulations can be used to determine a relation between bit-width, operating frequency, and input signal conditions, for example.Type: GrantFiled: December 23, 2009Date of Patent: May 27, 2014Assignee: Indian Institute of ScienceInventors: Bharadwaj Amrutur, Satyam Dwivedi, Navakanta Bhat
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Patent number: 8702931Abstract: Design of a disposable screen printed electrode (SPE) for sensing percentage glycated hemoglobin using electrochemistry is disclosed. SPE has four electrodes, one working electrode for the detection of glycated hemoglobin, one working electrode for the detection of hemoglobin and the other two electrodes are counter and reference electrodes that are common for both detection schemes. It also has a cellulose acetate membrane with lysis agents and surfactant embedded in it. Lysis agents lyse erythrocytes and release hemoglobin. Surfactants modify hemoglobin structure and enhance the rate the electron transfer and thereby the output signal during the electrochemical analysis. The SPE is low cost and user friendly. The only input from the user is a drop of blood.Type: GrantFiled: April 18, 2012Date of Patent: April 22, 2014Assignee: Indian Institute of ScienceInventors: Siva Rama Krishna Vanjari, Navakanta Bhat, Sampath Srinivasan, Bharadwaj Amrutur, Chakrapani Kalapu, Amit Kumar Mandal
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Patent number: 8459128Abstract: The present invention relates to high sensitivity elastic deflection sensors, more particularly related to capacitively coupled FET based elastic deflection sensors. A sub-threshold elastic deflection FET sensor for sensing pressure/force comprises an elastic member forming a moving gate of the sensor, fixed dielectric on substrate of the FET, and a fluid dielectric between the elastic member and the fixed dielectric, wherein alteration in the height of the fluid dielectric (TSENS) due to pressure/force on the elastic member varies the sensor gate capacitance.Type: GrantFiled: June 19, 2008Date of Patent: June 11, 2013Assignee: Indian Institute of ScienceInventors: Navakanta Bhat, Rudra Pratap, Malhi Charanjeet Kaur
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Patent number: 8434374Abstract: The present invention relates to a Sub-threshold Field Effect Transistor (SF-FET). The invention integrates a MEMS mechanical transducer along with the sensing mechanism in a single device. Forced mass is capacitively coupled onto the FET structure. Dielectric SiO2 forms good interface with underlying silicon substrate. Air dielectric forms second dielectric wherein effective gate capacitance is the series combination of the second dielectric capacitance and fixed dielectric. Inertial displacements are sensed by observing change in drain current (ID) of the sensor due to change in gap height (TGap) of the second dielectric of the sensor caused by forced mass.Type: GrantFiled: June 19, 2008Date of Patent: May 7, 2013Assignee: Indian Institute of ScienceInventors: Navakanta Bhat, Rudra Pratap, Thejas
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Publication number: 20120264137Abstract: A porous membrane for lysis of a cell population enriched from a biological sample, and isolation of cellular components is provided. The porous membrane contains embedded lysing agents to perform lysing. The biological sample is brought into contact with the membrane. Lysis occurs through the action of the embedded lysing agents on the biological sample. The pores of the porous membrane are designed to have dimensions to allow only a desired type of cellular component(s) resulting from lysis to pass through the membrane, thereby achieving isolation of the desired cellular component(s). The action of lysing agents is combined with the filtration properties of porous membranes resulting in an easy-to-use and cost-effective technique.Type: ApplicationFiled: April 18, 2012Publication date: October 18, 2012Applicant: INDIAN INSTITUTE OF SCIENCEInventors: Siva Rama Krishna Vanjari, Navakanta Bhat, Sampath Srinivasan, Bharadwaj Amrutur, Sandeep Keshavan, Deepthi Indukuri
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Publication number: 20120261257Abstract: Design of a disposable screen printed electrode (SPE) for sensing percentage glycated hemoglobin using electrochemistry is disclosed. SPE has four electrodes, one working electrode for the detection of glycated hemoglobin, one working electrode for the detection of hemoglobin and the other two electrodes are counter and reference electrodes that are common for both detection schemes. It also has a cellulose acetate membrane with lysis agents and surfactant embedded in it. Lysis agents lyse erythrocytes and release hemoglobin. Surfactants modify hemoglobin structure and enhance the rate the electron transfer and thereby the output signal during the electrochemical analysis. The SPE is low cost and user friendly. The only input from the user is a drop of blood.Type: ApplicationFiled: April 18, 2012Publication date: October 18, 2012Applicant: INDIAN INSTITUTE OF SCIENCEInventors: Siva Rama Krishna Vanjari, Navakanta Bhat, Sampath Srinivasan, Bharadwaj Amrutur, Chakrapani Kalapu, Amit Kumar Mandal
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Publication number: 20120007586Abstract: A device and method for area sensing and actuation comprises highly scalable sensing and actuation network that can control a high density of sensing and actuation elements over a physical area. The device comprises a matrix of CMOS sensing chips that each comprise a plurality of sensing electrodes arranged in a matrix of columns and rows along horizontal wires and vertical wires. The vertical wires carry an activation signal to activate a column of sensing electrodes, and the vertical wires carry sensing and actuation signals between the column of sensing electrodes and a processing chip. The signals may be amplified by CMOS sensing chips between the source and destination of the signals. In this way, signals may be received from and sent to a dense matrix of sensing electrodes spanning a large geographic area with little or no degradation.Type: ApplicationFiled: August 26, 2010Publication date: January 12, 2012Applicant: INDIAN INSTITUTE OF SCIENCEInventors: Bharadwaj Amrutur, Navakanta Bhat
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Publication number: 20110096875Abstract: An adaptive digital baseband receiver is described in which operating parameters of the receiver, such as bit-widths and operating frequencies, are determined that achieve a target bit-error-ratio (BER) as a function of received signal-to-noise ratio (SNR) and interference levels in a wireless channel and enable the receiver to consume a minimum amount of power. Over consumption of power may be avoided due to a functional relationship between optimal resolution and input signal conditions. In exemplary embodiments, the adaptive digital receiver is provided that adjusts bit-widths and operating frequency at power efficient levels while meeting a target BER. Simulations can be used to determine a relation between bit-width, operating frequency, and input signal conditions, for example.Type: ApplicationFiled: December 23, 2009Publication date: April 28, 2011Inventors: Bharadwaj Amrutur, Satyam Dwivedi, Navakanta Bhat
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Publication number: 20110050201Abstract: The present invention relates to a Sub-threshold Field Effect Transistor (SF-FET). The invention integrates a MEMS mechanical transducer along with the sensing mechanism in a single device. Forced mass is capacitively coupled onto the FET structure. Dielectric SiO2 forms good interface with underlying silicon substrate. Air dielectric forms second dielectric wherein effective gate capacitance is the series combination of the second dielectric capacitance and fixed dielectric. Inertial displacements are sensed by observing change in drain current (ID) of the sensor due to change in gap height (T Gap) of the second dielectric of the sensor caused by forced mass.Type: ApplicationFiled: June 19, 2008Publication date: March 3, 2011Applicant: INDIAN INSTITUTE OF SCIENCEInventors: Navakanta Bhat, Rudra Pratap, Thejas
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Publication number: 20110031986Abstract: The present invention relates to high sensitivity chemical sensors, more particularly relates to high sensitivity chemical sensors which are capacitively coupled, FET based analyte sensors. A sub-threshold capacitively coupled Field Effect Transistor (CapFET) sensor for sensing an analyte comprises fixed dielectric placed on substrate of the CapFET and second dielectric sensitive to the analyte, placed between gate terminal of the CapFET and the fixed dielectric, wherein presence of the analyte alters either dielectric constant of the second dielectric or work function of the gate.Type: ApplicationFiled: June 19, 2008Publication date: February 10, 2011Inventors: Navakanta Bhat, Balaji Jayaraman, S.A. Shivashankar, Rudra Pratap
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Publication number: 20110023632Abstract: The present invention relates to high sensitivity elastic deflection sensors, more particularly related to capacitively coupled FET based elastic deflection sensors. A sub-threshold elastic deflection FET sensor for sensing pressure/force comprises an elastic member forming a moving gate of the sensor, fixed dielectric on substrate of the FET, and a fluid dielectric between the elastic member and the fixed dielectric, wherein alteration in the height of the fluid dielectric (TSENS) due to pressure/force on the elastic member varies the sensor gate capacitance.Type: ApplicationFiled: June 19, 2008Publication date: February 3, 2011Applicant: INDIAN INSTITUTE OF SCIENCEInventors: Navakanta Bhat, Rudra Pratap, Malhi Charanjeet Kaur
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Patent number: 7804330Abstract: The present invention provides an adaptive keeper circuit to control Domino Logic Dynamic Circuits using Rate Sensing Technique to provide reduced contention and efficient process tracking at given noise robustness with less overhead in area, power and delay, said adaptive keeper comprising, keeper PMOS transistor (M1), wherein the drain of M1 is connected to wide AND-OR logic circuit; the rate controller consisting of reference rate transistor (M4), feedback PMOS transistor (M2), feedback shutoff transistor (M5), clock shutoff transistor (M6), pre-charge PMOS transistor (M3), wherein the input of the rate controller is directly connected to drain of the keeper PMOS (M1) and the output of the rate controller is directly connected to the gate of the PMOS keeper (M1).Type: GrantFiled: June 26, 2007Date of Patent: September 28, 2010Assignee: Indian Institute of ScienceInventors: Navakanta Bhat, David Rakesh Gnana Jeyasingh
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Publication number: 20100073030Abstract: The present invention provides an adaptive keeper circuit to control Domino Logic Dynamic Circuits using Rate Sensing Technique to provide reduced contention and efficient process tracking at given noise robustness with less overhead in area, power and delay, said adaptive keeper comprising, keeper PMOS transistor (M1), wherein the drain of M1 is connected to wide AND-OR logic circuit; the rate controller consisting of reference rate transistor (M4), feedback PMOS transistor (M2), feed-back shutoff transistor (M5), clock shutoff transistor (M6), pre-charge PMOS transistor (M3), wherein the input of the rate controller is directly connected to drain of the keeper PMOS (M1) and the output of the rate controller is directly connected to the gate of the PMOS keeper (M1),Type: ApplicationFiled: June 26, 2007Publication date: March 25, 2010Inventors: Navakanta Bhat, David Rakesh Gnana
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Patent number: 6934200Abstract: A novel technique for the enhancement of yield and speed of semiconductor integrated circuits using post fabrication transistor mismatch compensation circuitry is provided. The system has a sense amplifier, a multiplexer, delay elements, and a provision for hardwiring fast and slow circuits during packaging of a memory circuit. The sense amplifier firing path is split into a slow and a fast path and the multiplexer can select either the slow path or fast path. The memory circuit is tested after fabrication to assess whether each memory cell can be identified as slow or fast circuits and accordingly the fast path or slow path is selected by the multiplexer. The path for each memory cell may be then hardwired during packaging by connecting a select input of multiplexer to a VDD signal or a ground signal.Type: GrantFiled: March 11, 2002Date of Patent: August 23, 2005Assignee: Indian Institute of ScienceInventors: Navakanta Bhat, Sugato Mukherjee