Patents by Inventor Navakanta Bhat

Navakanta Bhat has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170241945
    Abstract: An electrochemically active device is provided for collecting and retaining a blood sample with at least a two-electrode member connected to conductive tracks. A receptor with an integral receptor-membrane arranged on the two-electrode member, to receive non-electrochemically active heamoglobin bioanalyte and its complexes from red blood cells (RBC) of said blood sample, through a lysing agent and convert the non-electrochemically active heamoglobin bioanalyte and its complexes, into an electrochemically active bioanalyte and its electrochemically active complexes. The present invention also provides a point-of-care biosensor incorporated with the device of the present invention and method of measuring for the detection and quantitative measurement of concentrations of haemoglobin (Hb), glycated haemoglobin (GHb), methaemoglobin (MetHb) and myoglobin, in reduced volumes of blood samples, by determining redox current values in the reduced volumes of blood samples.
    Type: Application
    Filed: September 7, 2015
    Publication date: August 24, 2017
    Inventors: Vinay Kumar, Navakanta Bhat
  • Patent number: 9741656
    Abstract: The present invention provides a high-frequency integrated device, comprising a substrate including at least an on-chip active and passive member and a ferrite layer bonded to the substrate through an interfacial bridge and substantially wrapping plurality of surfaces of said at least on-chip active and passive members. The present invention also provides a system incorporating the high-frequency integrated device of the present invention. The present invention further provides a process for the preparation of the high-frequency integrated device.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: August 22, 2017
    Assignee: INDIAN INSTITUTE OF SCIENCE
    Inventors: Ranajit Sai, Srinivasarao Ajjampur Shivshankar, Navakanta Bhat, Vinoy Kalarickaparambil Joseph
  • Patent number: 9297671
    Abstract: A device and method for area sensing and actuation comprises highly scalable sensing and actuation network that can control a high density of sensing and actuation elements over a physical area. The device comprises a matrix of CMOS sensing chips that each comprise a plurality of sensing electrodes arranged in a matrix of columns and rows along horizontal wires and vertical wires. The vertical wires carry an activation signal to activate a column of sensing electrodes, and the vertical wires carry sensing and actuation signals between the column of sensing electrodes and a processing chip. The signals may be amplified by CMOS sensing chips between the source and destination of the signals. In this way, signals may be received from and sent to a dense matrix of sensing electrodes spanning a large geographic area with little or no degradation.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: March 29, 2016
    Assignee: INDIAN INSTITUTE OF SCIENCE
    Inventors: Bharadwaj Amrutur, Navakanta Bhat
  • Publication number: 20150369634
    Abstract: A device and method for area sensing and actuation comprises highly scalable sensing and actuation network that can control a high density of sensing and actuation elements over a physical area. The device comprises a matrix of CMOS sensing chips that each comprise a plurality of sensing electrodes arranged in a matrix of columns and rows along horizontal wires and vertical wires. The vertical wires carry an activation signal to activate a column of sensing electrodes, and the vertical wires carry sensing and actuation signals between the column of sensing electrodes and a processing chip. The signals may be amplified by CMOS sensing chips between the source and destination of the signals. In this way, signals may be received from and sent to a dense matrix of sensing electrodes spanning a large geographic area with little or no degradation.
    Type: Application
    Filed: September 1, 2015
    Publication date: December 24, 2015
    Inventors: BHARADWAJ AMRUTUR, NAVAKANTA BHAT
  • Patent number: 9158408
    Abstract: A device and method for area sensing and actuation comprises highly scalable sensing and actuation network that can control a high density of sensing and actuation elements over a physical area. The device comprises a matrix of CMOS sensing chips that each comprise a plurality of sensing electrodes arranged in a matrix of columns and rows along horizontal wires and vertical wires. The vertical wires carry an activation signal to activate a column of sensing electrodes, and the vertical wires carry sensing and actuation signals between the column of sensing electrodes and a processing chip. The signals may be amplified by CMOS sensing chips between the source and destination of the signals. In this way, signals may be received from and sent to a dense matrix of sensing electrodes spanning a large geographic area with little or no degradation.
    Type: Grant
    Filed: August 26, 2010
    Date of Patent: October 13, 2015
    Assignee: Indian Institute of Science
    Inventors: Bharadwaj Amrutur, Navakanta Bhat
  • Publication number: 20150287658
    Abstract: The present invention provides a high-frequency integrated device, comprising a substrate including at least an on-chip active and passive member and a ferrite layer bonded to the substrate through an interfacial bridge and substantially wrapping plurality of surfaces of said at least on-chip active and passive members. The present invention also provides a system incorporating the high-frequency integrated device of the present invention. The present invention further provides a process for the preparation of the high-frequency integrated device.
    Type: Application
    Filed: October 30, 2013
    Publication date: October 8, 2015
    Applicant: INDIAN INSTITUTE OF SCIENCE
    Inventors: Ranajit Sai, Srinivasarao Ajjampur Shivshankar, Navakanta Bhat, Vinoy Kalarickaparambil Joseph
  • Patent number: 8737547
    Abstract: An adaptive digital baseband receiver is described in which operating parameters of the receiver, such as bit-widths and operating frequencies, are determined that achieve a target bit-error-ratio (BER) as a function of received signal-to-noise ratio (SNR) and interference levels in a wireless channel and enable the receiver to consume a minimum amount of power. Over consumption of power may be avoided due to a functional relationship between optimal resolution and input signal conditions. In exemplary embodiments, the adaptive digital receiver is provided that adjusts bit-widths and operating frequency at power efficient levels while meeting a target BER. Simulations can be used to determine a relation between bit-width, operating frequency, and input signal conditions, for example.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: May 27, 2014
    Assignee: Indian Institute of Science
    Inventors: Bharadwaj Amrutur, Satyam Dwivedi, Navakanta Bhat
  • Patent number: 8702931
    Abstract: Design of a disposable screen printed electrode (SPE) for sensing percentage glycated hemoglobin using electrochemistry is disclosed. SPE has four electrodes, one working electrode for the detection of glycated hemoglobin, one working electrode for the detection of hemoglobin and the other two electrodes are counter and reference electrodes that are common for both detection schemes. It also has a cellulose acetate membrane with lysis agents and surfactant embedded in it. Lysis agents lyse erythrocytes and release hemoglobin. Surfactants modify hemoglobin structure and enhance the rate the electron transfer and thereby the output signal during the electrochemical analysis. The SPE is low cost and user friendly. The only input from the user is a drop of blood.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: April 22, 2014
    Assignee: Indian Institute of Science
    Inventors: Siva Rama Krishna Vanjari, Navakanta Bhat, Sampath Srinivasan, Bharadwaj Amrutur, Chakrapani Kalapu, Amit Kumar Mandal
  • Patent number: 8459128
    Abstract: The present invention relates to high sensitivity elastic deflection sensors, more particularly related to capacitively coupled FET based elastic deflection sensors. A sub-threshold elastic deflection FET sensor for sensing pressure/force comprises an elastic member forming a moving gate of the sensor, fixed dielectric on substrate of the FET, and a fluid dielectric between the elastic member and the fixed dielectric, wherein alteration in the height of the fluid dielectric (TSENS) due to pressure/force on the elastic member varies the sensor gate capacitance.
    Type: Grant
    Filed: June 19, 2008
    Date of Patent: June 11, 2013
    Assignee: Indian Institute of Science
    Inventors: Navakanta Bhat, Rudra Pratap, Malhi Charanjeet Kaur
  • Patent number: 8434374
    Abstract: The present invention relates to a Sub-threshold Field Effect Transistor (SF-FET). The invention integrates a MEMS mechanical transducer along with the sensing mechanism in a single device. Forced mass is capacitively coupled onto the FET structure. Dielectric SiO2 forms good interface with underlying silicon substrate. Air dielectric forms second dielectric wherein effective gate capacitance is the series combination of the second dielectric capacitance and fixed dielectric. Inertial displacements are sensed by observing change in drain current (ID) of the sensor due to change in gap height (TGap) of the second dielectric of the sensor caused by forced mass.
    Type: Grant
    Filed: June 19, 2008
    Date of Patent: May 7, 2013
    Assignee: Indian Institute of Science
    Inventors: Navakanta Bhat, Rudra Pratap, Thejas
  • Publication number: 20120264137
    Abstract: A porous membrane for lysis of a cell population enriched from a biological sample, and isolation of cellular components is provided. The porous membrane contains embedded lysing agents to perform lysing. The biological sample is brought into contact with the membrane. Lysis occurs through the action of the embedded lysing agents on the biological sample. The pores of the porous membrane are designed to have dimensions to allow only a desired type of cellular component(s) resulting from lysis to pass through the membrane, thereby achieving isolation of the desired cellular component(s). The action of lysing agents is combined with the filtration properties of porous membranes resulting in an easy-to-use and cost-effective technique.
    Type: Application
    Filed: April 18, 2012
    Publication date: October 18, 2012
    Applicant: INDIAN INSTITUTE OF SCIENCE
    Inventors: Siva Rama Krishna Vanjari, Navakanta Bhat, Sampath Srinivasan, Bharadwaj Amrutur, Sandeep Keshavan, Deepthi Indukuri
  • Publication number: 20120261257
    Abstract: Design of a disposable screen printed electrode (SPE) for sensing percentage glycated hemoglobin using electrochemistry is disclosed. SPE has four electrodes, one working electrode for the detection of glycated hemoglobin, one working electrode for the detection of hemoglobin and the other two electrodes are counter and reference electrodes that are common for both detection schemes. It also has a cellulose acetate membrane with lysis agents and surfactant embedded in it. Lysis agents lyse erythrocytes and release hemoglobin. Surfactants modify hemoglobin structure and enhance the rate the electron transfer and thereby the output signal during the electrochemical analysis. The SPE is low cost and user friendly. The only input from the user is a drop of blood.
    Type: Application
    Filed: April 18, 2012
    Publication date: October 18, 2012
    Applicant: INDIAN INSTITUTE OF SCIENCE
    Inventors: Siva Rama Krishna Vanjari, Navakanta Bhat, Sampath Srinivasan, Bharadwaj Amrutur, Chakrapani Kalapu, Amit Kumar Mandal
  • Publication number: 20120007586
    Abstract: A device and method for area sensing and actuation comprises highly scalable sensing and actuation network that can control a high density of sensing and actuation elements over a physical area. The device comprises a matrix of CMOS sensing chips that each comprise a plurality of sensing electrodes arranged in a matrix of columns and rows along horizontal wires and vertical wires. The vertical wires carry an activation signal to activate a column of sensing electrodes, and the vertical wires carry sensing and actuation signals between the column of sensing electrodes and a processing chip. The signals may be amplified by CMOS sensing chips between the source and destination of the signals. In this way, signals may be received from and sent to a dense matrix of sensing electrodes spanning a large geographic area with little or no degradation.
    Type: Application
    Filed: August 26, 2010
    Publication date: January 12, 2012
    Applicant: INDIAN INSTITUTE OF SCIENCE
    Inventors: Bharadwaj Amrutur, Navakanta Bhat
  • Publication number: 20110096875
    Abstract: An adaptive digital baseband receiver is described in which operating parameters of the receiver, such as bit-widths and operating frequencies, are determined that achieve a target bit-error-ratio (BER) as a function of received signal-to-noise ratio (SNR) and interference levels in a wireless channel and enable the receiver to consume a minimum amount of power. Over consumption of power may be avoided due to a functional relationship between optimal resolution and input signal conditions. In exemplary embodiments, the adaptive digital receiver is provided that adjusts bit-widths and operating frequency at power efficient levels while meeting a target BER. Simulations can be used to determine a relation between bit-width, operating frequency, and input signal conditions, for example.
    Type: Application
    Filed: December 23, 2009
    Publication date: April 28, 2011
    Inventors: Bharadwaj Amrutur, Satyam Dwivedi, Navakanta Bhat
  • Publication number: 20110050201
    Abstract: The present invention relates to a Sub-threshold Field Effect Transistor (SF-FET). The invention integrates a MEMS mechanical transducer along with the sensing mechanism in a single device. Forced mass is capacitively coupled onto the FET structure. Dielectric SiO2 forms good interface with underlying silicon substrate. Air dielectric forms second dielectric wherein effective gate capacitance is the series combination of the second dielectric capacitance and fixed dielectric. Inertial displacements are sensed by observing change in drain current (ID) of the sensor due to change in gap height (T Gap) of the second dielectric of the sensor caused by forced mass.
    Type: Application
    Filed: June 19, 2008
    Publication date: March 3, 2011
    Applicant: INDIAN INSTITUTE OF SCIENCE
    Inventors: Navakanta Bhat, Rudra Pratap, Thejas
  • Publication number: 20110031986
    Abstract: The present invention relates to high sensitivity chemical sensors, more particularly relates to high sensitivity chemical sensors which are capacitively coupled, FET based analyte sensors. A sub-threshold capacitively coupled Field Effect Transistor (CapFET) sensor for sensing an analyte comprises fixed dielectric placed on substrate of the CapFET and second dielectric sensitive to the analyte, placed between gate terminal of the CapFET and the fixed dielectric, wherein presence of the analyte alters either dielectric constant of the second dielectric or work function of the gate.
    Type: Application
    Filed: June 19, 2008
    Publication date: February 10, 2011
    Inventors: Navakanta Bhat, Balaji Jayaraman, S.A. Shivashankar, Rudra Pratap
  • Publication number: 20110023632
    Abstract: The present invention relates to high sensitivity elastic deflection sensors, more particularly related to capacitively coupled FET based elastic deflection sensors. A sub-threshold elastic deflection FET sensor for sensing pressure/force comprises an elastic member forming a moving gate of the sensor, fixed dielectric on substrate of the FET, and a fluid dielectric between the elastic member and the fixed dielectric, wherein alteration in the height of the fluid dielectric (TSENS) due to pressure/force on the elastic member varies the sensor gate capacitance.
    Type: Application
    Filed: June 19, 2008
    Publication date: February 3, 2011
    Applicant: INDIAN INSTITUTE OF SCIENCE
    Inventors: Navakanta Bhat, Rudra Pratap, Malhi Charanjeet Kaur
  • Patent number: 7804330
    Abstract: The present invention provides an adaptive keeper circuit to control Domino Logic Dynamic Circuits using Rate Sensing Technique to provide reduced contention and efficient process tracking at given noise robustness with less overhead in area, power and delay, said adaptive keeper comprising, keeper PMOS transistor (M1), wherein the drain of M1 is connected to wide AND-OR logic circuit; the rate controller consisting of reference rate transistor (M4), feedback PMOS transistor (M2), feedback shutoff transistor (M5), clock shutoff transistor (M6), pre-charge PMOS transistor (M3), wherein the input of the rate controller is directly connected to drain of the keeper PMOS (M1) and the output of the rate controller is directly connected to the gate of the PMOS keeper (M1).
    Type: Grant
    Filed: June 26, 2007
    Date of Patent: September 28, 2010
    Assignee: Indian Institute of Science
    Inventors: Navakanta Bhat, David Rakesh Gnana Jeyasingh
  • Publication number: 20100073030
    Abstract: The present invention provides an adaptive keeper circuit to control Domino Logic Dynamic Circuits using Rate Sensing Technique to provide reduced contention and efficient process tracking at given noise robustness with less overhead in area, power and delay, said adaptive keeper comprising, keeper PMOS transistor (M1), wherein the drain of M1 is connected to wide AND-OR logic circuit; the rate controller consisting of reference rate transistor (M4), feedback PMOS transistor (M2), feed-back shutoff transistor (M5), clock shutoff transistor (M6), pre-charge PMOS transistor (M3), wherein the input of the rate controller is directly connected to drain of the keeper PMOS (M1) and the output of the rate controller is directly connected to the gate of the PMOS keeper (M1),
    Type: Application
    Filed: June 26, 2007
    Publication date: March 25, 2010
    Inventors: Navakanta Bhat, David Rakesh Gnana
  • Patent number: 6934200
    Abstract: A novel technique for the enhancement of yield and speed of semiconductor integrated circuits using post fabrication transistor mismatch compensation circuitry is provided. The system has a sense amplifier, a multiplexer, delay elements, and a provision for hardwiring fast and slow circuits during packaging of a memory circuit. The sense amplifier firing path is split into a slow and a fast path and the multiplexer can select either the slow path or fast path. The memory circuit is tested after fabrication to assess whether each memory cell can be identified as slow or fast circuits and accordingly the fast path or slow path is selected by the multiplexer. The path for each memory cell may be then hardwired during packaging by connecting a select input of multiplexer to a VDD signal or a ground signal.
    Type: Grant
    Filed: March 11, 2002
    Date of Patent: August 23, 2005
    Assignee: Indian Institute of Science
    Inventors: Navakanta Bhat, Sugato Mukherjee