Abstract: A novel technique for the enhancement of yield and speed of semiconductor integrated circuits using post fabrication transistor mismatch compensation circuitry is proposed. The system is novel because it recognizes that no matter what, the transistor mismatch is statistical in nature and hence it is prudent to exploit the nature of the distribution to get fast and slow circuits rather than make all circuits slow to meet 6&sgr; design index. The system comprises of sense amplifier, multiplexer, delay elements, and provision for hardwiring fast and slow circuits during packaging. The sense amplifier firing path is split into slow and fast path and the multiplexer can select one of these. The memory circuits are tested after fabrication to assess whether they could be partitioned as slow or fast circuits and accordingly an appropriate path is selected by the multiplexer. This path is then hardwired during packaging by connecting the select input of multiplexer to VDD or GND.

Abstract: A first dielectric layer (22) is formed over a semiconductor device substrate. A resist layer (32) is then patterned to expose portions of the first dielectric layer (22). Portions of the first dielectric layer (22) are removed to expose portions of the semiconductor device substrate (42). The resist layer (32) is then removed. The semiconductor device substrate is cleaned without using a fluorine-containing solution and a second dielectric layer (62) is formed overlying the semiconductor device substrate.

Abstract: A method for forming a dual gate oxide (DGO) structure begins by forming a first oxide layer (106) within active areas (110) and (112). A protection layer (108a) is then formed over the layer (106). A mask (114) is used to allow removal of the layers (106 and 108a) from the active area (110). A thermal oxidation process is then used to form a thin second oxide layer (118) within an active area (110). Conductive gate electrodes (120a and 120b) are then formed wherein the first oxide layer (106) and the protection layer (108c) are incorporated into the gate dielectric layer of an MOS transistor (122a). The transistor (122b) has a thinner gate oxide layer that excludes the protection layer (108c).