Patents by Inventor Navneet Dour
Navneet Dour has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11722128Abstract: An apparatus is provided, where the apparatus includes a plurality of components; a first circuitry to generate a clock signal, and to supply the clock signal to the plurality of components; a second circuitry to estimate, for each of two or more components of the plurality of components, a corresponding duty cycle of the clock signal received at the corresponding component, wherein two or more duty cycles corresponding to the two or more components are determined; a third circuitry to determine an average of the two or more duty cycles; and a fourth circuitry to correct a duty cycle of the clock signal generated by the first circuitry, based at least in part on the average.Type: GrantFiled: June 24, 2021Date of Patent: August 8, 2023Assignee: Intel CorporationInventors: Aaron Martin, Roger Cheng, Hari Venkatramani, Navneet Dour, Mozhgan Mansuri, Bryan Casper, Frank O'Mahony, Ganesh Balamurugan, Ajay Balankutty, Kuan Zhou, Sridhar Tirumalai, Krishnamurthy Venkataramana, Alex Thomas, Quoc Nguyen
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Publication number: 20210320652Abstract: An apparatus is provided, where the apparatus includes a plurality of components; a first circuitry to generate a clock signal, and to supply the clock signal to the plurality of components; a second circuitry to estimate, for each of two or more components of the plurality of components, a corresponding duty cycle of the clock signal received at the corresponding component, wherein two or more duty cycles corresponding to the two or more components are determined; a third circuitry to determine an average of the two or more duty cycles; and a fourth circuitry to correct a duty cycle of the clock signal generated by the first circuitry, based at least in part on the average.Type: ApplicationFiled: June 24, 2021Publication date: October 14, 2021Applicant: Intel CorporationInventors: Aaron Martin, Roger Cheng, Hari Venkatramani, Navneet Dour, Mozhgan Mansuri, Bryan Casper, Frank O'Mahony, Ganesh Balamurugan, Ajay Balankutty, Kuan Zhou, Sridhar Tirumalai, Krishnamurthy Venkataramana, Alex Thomas, Quoc Nguyen
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Patent number: 11070200Abstract: An apparatus is provided, where the apparatus includes a plurality of components; a first circuitry to generate a clock signal, and to supply the clock signal to the plurality of components; a second circuitry to estimate, for each of two or more components of the plurality of components, a corresponding duty cycle of the clock signal received at the corresponding component, wherein two or more duty cycles corresponding to the two or more components are determined; a third circuitry to determine an average of the two or more duty cycles; and a fourth circuitry to correct a duty cycle of the clock signal generated by the first circuitry, based at least in part on the average.Type: GrantFiled: September 27, 2018Date of Patent: July 20, 2021Assignee: Intel CorporationInventors: Aaron Martin, Roger Cheng, Hari Venkatramani, Navneet Dour, Mozhgan Mansuri, Bryan Casper, Frank O'Mahony, Ganesh Balamurugan, Ajay Balankutty, Kuan Zhou, Sridhar Tirumalai, Krishnamurthy Venkataramana, Alex Thomas, Quoc Nguyen
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Patent number: 11042315Abstract: In a computer system, a multilevel memory includes a near memory device and a far memory device, which are byte addressable. The multilevel memory includes a controller that receives a data request including original tag information. The controller includes routing hardware to selectively provide alternate tag information for the data request to cause a cache hit or a cache miss to selectively direct the request to the near memory device or to the far memory device, respectively. The controller can include selection circuitry to select between the original tag information and the alternate tag information to control where the data request is sent.Type: GrantFiled: March 29, 2018Date of Patent: June 22, 2021Assignee: Intel CorporationInventors: Lakshminarayana Pappu, Christopher E. Cox, Navneet Dour, Asaf Rubinstein, Israel Diamand
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Patent number: 10613955Abstract: A system includes test control circuitry in parallel with power control circuitry. The power control circuitry enables a core processor and memory interface drivers responsive to a reset. The test control circuitry can enable the memory interface drivers separately from the core processor to enable testing of the connections to the memory devices. The test control circuitry is triggered separately from the other power control circuitry, and can be protected to allow only secured access for testing.Type: GrantFiled: December 28, 2017Date of Patent: April 7, 2020Assignee: Intel CorporationInventors: Lakshminarayana Pappu, Navneet Dour, Christopher E. Cox
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Publication number: 20200106430Abstract: An apparatus is provided, where the apparatus includes a plurality of components; a first circuitry to generate a clock signal, and to supply the clock signal to the plurality of components; a second circuitry to estimate, for each of two or more components of the plurality of components, a corresponding duty cycle of the clock signal received at the corresponding component, wherein two or more duty cycles corresponding to the two or more components are determined; a third circuitry to determine an average of the two or more duty cycles; and a fourth circuitry to correct a duty cycle of the clock signal generated by the first circuitry, based at least in part on the average.Type: ApplicationFiled: September 27, 2018Publication date: April 2, 2020Applicant: Intel CorporationInventors: Aaron Martin, Roger Cheng, Hari Venkatramani, Navneet Dour, Mozhgan Mansuri, Bryan Casper, Frank O'Mahony, Ganesh Balamurugan, Ajay Balankutty, Kuan Zhou, Sridhar Tirumalai, Krishnamurthy Venkataramana, Alex Thomas, Quoc Nguyen
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Publication number: 20190042382Abstract: A system includes test control circuitry in parallel with power control circuitry. The power control circuitry enables a core processor and memory interface drivers responsive to a reset. The test control circuitry can enable the memory interface drivers separately from the core processor to enable testing of the connections to the memory devices. The test control circuitry is triggered separately from the other power control circuitry, and can be protected to allow only secured access for testing.Type: ApplicationFiled: December 28, 2017Publication date: February 7, 2019Inventors: Lakshminarayana PAPPU, Navneet DOUR, Christopher E. COX
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Publication number: 20190042131Abstract: In a computer system, a multilevel memory includes a near memory device and a far memory device, which are byte addressable. The multilevel memory includes a controller that receives a data request including original tag information. The controller includes routing hardware to selectively provide alternate tag information for the data request to cause a cache hit or a cache miss to selectively direct the request to the near memory device or to the far memory device, respectively. The controller can include selection circuitry to select between the original tag information and the alternate tag information to control where the data request is sent.Type: ApplicationFiled: March 29, 2018Publication date: February 7, 2019Inventors: Lakshminarayana PAPPU, Christopher E. COX, Navneet DOUR, Asaf RUBINSTEIN, Israel DIAMAND
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Patent number: 7751274Abstract: Some embodiments are directed to circuits comprising first and second PLLs. The first PLL generates a first clock signal based on a reference clock signal. The second PLL generates a second clock signal based on the reference clock signal and is synchronized with the first clock signal.Type: GrantFiled: September 5, 2006Date of Patent: July 6, 2010Assignee: Intel CorporationInventors: Navneet Dour, Joe H. Salmon
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Patent number: 7746135Abstract: Disclosed herein is a wake-up circuit for a bias input of a circuit such as a slave DLL circuit, to allow it to be placed in a reduced power mode and be “awoken” (brought up to a control bias level) in a sufficiently small enough amount of time. The wake-up circuit couples a bias input node to a voltage level that is higher then the control bias level in response to a wake-up event, and then it couples the control bias node to the bias input node in response to their voltage levels being sufficiently close to one another.Type: GrantFiled: September 29, 2007Date of Patent: June 29, 2010Assignee: Intel CorporationInventors: Jacob S. Schneider, Navneet Dour, Harishankar Sridharan
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Patent number: 7602859Abstract: An embodiment of the present invention is a technique to calibrate an integrating receiver. A delay calibration circuit calibrates an adjusting code of a chain of delay elements and positioning of at least an integrating strobe used to define an integration window for the integrating receiver. An integrating receiver pulse generator generates an IR pulse from the at least integrating strobe. A calibration controller controls calibrating the adjusting code and the positioning of the at least integrating strobe.Type: GrantFiled: April 28, 2005Date of Patent: October 13, 2009Assignee: Intel CorporationInventors: Roger K. Cheng, Harishankar Sridharan, Navneet Dour, Hing Y. To
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Publication number: 20090085618Abstract: Disclosed herein is a wake-up circuit for a bias input of a circuit such as a slave DLL circuit, to allow it to be placed in a reduced power mode and be “awoken” (brought up to a control bias level) in a sufficiently small enough amount of time. The wake-up circuit couples a bias input node to a voltage level that is higher then the control bias level in response to a wake-up event, and then it couples the control bias node to the bias input node in response to their voltage levels being sufficiently close to one another.Type: ApplicationFiled: September 29, 2007Publication date: April 2, 2009Inventors: Jacob S. Schneider, Navneet Dour, Harishankar Sridharan
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Patent number: 7432731Abstract: An embodiment may comprise memory with a memory array, a resistor coupled to a reference voltage, on die termination circuitry coupled with the resistor, and an input coupled to the on die termination circuitry and coupled with the memory array, the input to receive a calibration command to stop use of the input and the memory array and calibrate the on die termination circuitry with the resistor coupled to the reference voltage. Other embodiments are disclosed herein.Type: GrantFiled: June 30, 2005Date of Patent: October 7, 2008Assignee: Intel CorporationInventors: Kuljit S. Bains, Navneet Dour, Hany Fahmy, George Vergis, Christopher E. Cox
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Patent number: 7403034Abstract: Embodiments include an on die termination circuit. The on die termination circuit may be programmable. The on die termination circuit may be programmed to compensate for environmental conditions and the physical characteristics of the device. The programmed on die termination circuit allows for faster transfer rates over communication lines by reducing the time needed to recover from signal reflection and similar issues.Type: GrantFiled: January 19, 2006Date of Patent: July 22, 2008Assignee: Intel CorporationInventors: Navneet Dour, Roger K. Cheng
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Publication number: 20080065922Abstract: Disclosed herein are methods and circuits to generate a clock signal.Type: ApplicationFiled: September 5, 2006Publication date: March 13, 2008Inventors: Navneet Dour, Joe H. Salmon
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Patent number: 7307900Abstract: To allow a memory controller to synchronize strobe to clock relationship for a DRAM, a register, such as, a flip flop, is incorporated within the DRAM to facilitate the sampling of SCLK with DQS. Likewise, while the DRAM is in a test mode of operation, the memory controller advances or retards the clock to DQS at the memory controller hub (MCH) to achieve the proper DRAM relationship. In one embodiment, the memory controller advances DQS if a binary zero value is read. In contrast, the memory controller retards DQS if a binary one value is read.Type: GrantFiled: November 30, 2004Date of Patent: December 11, 2007Assignee: Intel CorporationInventors: Joe Salmon, Navneet Dour, George Vergis
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Publication number: 20070007992Abstract: An embodiment may comprise memory with a memory array, a resistor coupled to a reference voltage, on die termination circuitry coupled with the resistor, and an input coupled to the on die termination circuitry and coupled with the memory array, the input to receive a calibration command to stop use of the input and the memory array and calibrate the on die termination circuitry with the resistor coupled to the reference voltage. Other embodiments are disclosed herein.Type: ApplicationFiled: June 30, 2005Publication date: January 11, 2007Inventors: Kuljit Bains, Navneet Dour, Hany Fahmy, George Vergis, Christopher Cox
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Publication number: 20060245519Abstract: An embodiment of the present invention is a technique to calibrate an integrating receiver. A delay calibration circuit calibrates an adjusting code of a chain of delay elements and positioning of at least an integrating strobe used to define an integration window for the integrating receiver. An integrating receiver calibration pulse generator generates an IR calibration pulse from the at least integrating strobe. A calibration controller controls calibrating the adjusting code and the positioning of the at least integrating strobe.Type: ApplicationFiled: April 28, 2005Publication date: November 2, 2006Inventors: Roger Cheng, Harishankar Sridharan, Navneet Dour, Hing To
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Publication number: 20060245473Abstract: An embodiment of the present invention is a technique to integrate data for a source synchronous protocol. A delay generator generates at least an integrating strobe from a data strobe synchronizing a data having a data window using the source synchronous protocol. A pulse generator generates a pulse from the at least integrating strobe. An integrating receiver integrates the data over an integration window defined by the pulse. The integration window is within the data window.Type: ApplicationFiled: April 28, 2005Publication date: November 2, 2006Inventors: Roger Cheng, Navneet Dour, Scott Miller, David Freker, Harishankar Sridharan, Mahmood Alam
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Publication number: 20060119381Abstract: Embodiments include an on die termination circuit. The on die termination circuit may be programmable. The on die termination circuit may be programmed to compensate for environmental conditions and the physical characteristics of the device. The programmed on die termination circuit allows for faster transfer rates over communication lines by reducing the time needed to recover from signal reflection and similar issues.Type: ApplicationFiled: January 19, 2006Publication date: June 8, 2006Inventors: Navneet Dour, Roger Cheng