Abstract: To allow a memory controller to synchronize strobe to clock relationship for a DRAM, a register, such as, a flip flop, is incorporated within the DRAM to facilitate the sampling of SCLK with DQS. Likewise, while the DRAM is in a test mode of operation, the memory controller advances or retards the clock to DQS at the memory controller hub (MCH) to achieve the proper DRAM relationship. In one embodiment, the memory controller advances DQS if a binary zero value is read. In contrast, the memory controller retards DQS if a binary one value is read.

Abstract: Embodiments include an on die termination circuit. The on die termination circuit may be programmable. The on die termination circuit may be programmed to compensate for environmental conditions and the physical characteristics of the device. The programmed on die termination circuit allows for faster transfer rates over communication lines by reducing the time needed to recover from signal reflection and similar issues.

Abstract: In one embodiment, a pre-driver generates pre-driving signals based on control signals provided by a control circuit. The pre-driver has pre-driver power and ground connections. The pre-driving signals operate at a frequency band. A driver generates an output signal based on the pre-driving signals at an output pad. The output signal has a slew rate. The driver has driver power and ground connections. A low pass filter is coupled between the pre-driver and the driver power and ground connections to reduce the effect of noise at the pre-driving signals. The low pass filter has a cut-off frequency corresponding to the frequency of noise. In another embodiment, a plurality of pre-drivers generates pre-driving signals based on control signals provided by a control circuit. The pre-drivers have pre-driver power and ground connections. A plurality of drivers generates a plurality of output signals based on the pre-driving signals at output pads of an integrated circuit. Each of the output signals has a slew rate.

Abstract: A method is described that involves, for a first read of information from a memory, activating termination loads on a memory controller's side of a data bus between a memory controller and a memory. The method also involves, for a write of information into the memory, deactivating the termination loads. The method also involves, for a second read of information from the memory, activating the termination loads.

Abstract: Apparatus and method to vary the strength with which a signal transmitted by a driver circuit of a transmitting device to a receiving circuit across a conductor such that a transmitted voltage level is driven onto a conductor with a reduced strength where adjacent binary bits values are of the same value so as to avoid building up capacitive a charge of either an undesirably high or undesirably low voltage level as a result of continuing to drive the same voltage level with the same strength, and such that a transmitted voltage level is driven onto a conductor with a greater strength where the voltage level now being transmitted differs from the previous voltage level so as to overcome the capacitive charge of the previous voltage level that may have built up, more quickly.

Abstract: Embodiments include an on die termination circuit. The on die termination circuit may be programmable. The on die termination circuit may be programmed to compensate for environmental conditions and the physical characteristics of the device. The programmed on die termination circuit allows for faster transfer rates over communication lines by reducing the time needed to recover from signal reflection and similar issues.

Abstract: A method is described that involves, for a first read of information from a memory, activating termination loads on a memory controller's side of a data bus between a memory controller and a memory. The method also involves, for a write of information into the memory, deactivating the termination loads. The method also involves, for a second read of information from the memory, activating the termination loads.

Abstract: In one embodiment, a pre-driver generates pre-driving signals based on control signals provided by a control circuit. The pre-driver has pre-driver power and ground connections. The pre-driving signals operate at a frequency band. A driver generates an output signal based on the pre-driving signals at an output pad. The output signal has a slew rate. The driver has driver power and ground connections. A low pass filter is coupled between the pre-driver and the driver power and ground connections to reduce the effect of noise at the pre-driving signals. The low pass filter has a cut-off frequency corresponding to the frequency of noise. In another embodiment, a plurality of pre-drivers generates pre-driving signals based on control signals provided by a control circuit. The pre-drivers have pre-driver power and ground connections. A plurality of drivers generates a plurality of output signals based on the pre-driving signals at output pads of an integrated circuit. Each of the output signals has a slew rate.

Abstract: In one embodiment, a pre-driver generates pre-driving signals based on control signals provided by a control circuit. The pre-driver has pre-driver power and ground connections. The pre-driving signals operate at a frequency band. A driver generates an output signal based on the pre-driving signals at an output pad. The output signal has a slew rate. The driver has driver power and ground connections. A low pass filter is coupled between the pre-driver and the driver power and ground connections to reduce the effect of noise at the pre-driving signals. The low pass filter has a cut-off frequency corresponding to the frequency of noise. In another embodiment, a plurality of pre-drivers generates pre-driving signals based on control signals provided by a control circuit. The pre-drivers have pre-driver power and ground connections. A plurality of drivers generates a plurality of output signals based on the pre-driving signals at output pads of an integrated circuit. Each of the output signals has a slew rate.

Abstract: In one embodiment, a driver impedance control mechanism is adapted for a circuit board. The driver impedance control mechanism comprises (i) an integrated circuit including at least one driver circuit operating as a pull-up driver and a pull-down driver, (ii) a link coupled to an interface pin of the integrated circuit, the interface pin receiving signals from the at least one driver circuit, and (iii) a single resistive element terminating the link and separately compensating the at least one driver when operating as the pull-up driver and the pull-down driver and supplying the same impedance control bits to all driver to have good signal quality over the interface.

Abstract: In one embodiment, a pre-driver generates pre-driving signals based on control signals provided by a control circuit. The pre-driver has pre-driver power and ground connections. The pre-driving signals operate at a frequency band. A driver generates an output signal based on the pre-driving signals at an output pad. The output signal has a slew rate. The driver has driver power and ground connections. A low pass filter is coupled between the pre-driver and the driver power and ground connections to reduce the effect of noise at the pre-driving signals. The low pass filter has a cut-off frequency corresponding to the frequency of noise. In another embodiment, a plurality of pre-drivers generates pre-driving signals based on control signals provided by a control circuit. The pre-drivers have pre-driver power and ground connections. A plurality of drivers generates a plurality of output signals based on the pre-driving signals at output pads of an integrated circuit. Each of the output signals has a slew rate.

Abstract: In one embodiment, a driver impedance control mechanism is adapted for a circuit board. The driver impedance control mechanism comprises (i) an integrated circuit including at least one driver circuit operating as a pull-up driver and a pull-down driver, (ii) a link coupled to an interface pin of the integrated circuit, the interface pin receiving signals from the at least one driver circuit, and (iii) a single resistive element terminating the link and separately compensating the at least one driver when operating as the pull-up driver and the pull-down driver and supplying the same impedance control bits to all driver to have good signal quality over the interface.

Abstract: A differential amplifier power supply is derived from the same source that generates the reference voltage for the differential amplifiers. This will ensure the direction of voltage level shifts of these two voltages to be in tandem. That is, these two voltages will move in the same direction due to any variations in the source since they are generated from the same regulator. In this way receiver timing errors can be significantly reduced in source synchronous and common clock interfaces.

Abstract: A power-up circuit for a multi-voltage chip having two or more electrostatic devices coupled in series between first and second power supply lines, with a first electrostatic device being coupled between a node and the second power supply line. The power-up circuit comprising a MOS transistor coupled between the first power supply line and the node. A voltage divider coupled between the first and second power supply lines controls the conductivity of the MOS transistor. An internal node of the voltage divider is coupled to the gate of the MOS transistor and the divider is configured such that the internal node rises in potential following power-up to regulate the conductivity of the MOS transistor. The MOS transistor changes from a high conducting state to a low conducting state responsive to an increase in potential of the second power supply line following power-up.