Abstract: A controllable voltage source (902) is coupled to a microelectronic circuit (901) for providing an operating voltage. Said microelectronic circuit (901) is adaptive, so its performance is at least partly configurable by value of said operating voltage. The operating voltage is regulated into conformity with a target value. Reregulating said operating voltage into conformity with a new target value involves a time constant. On a processing path a first register circuit (502) comprises a data input coupled to an output of a preceding first logic unit (501). The microelectronic circuit (901) responds to a digital value at said data input changing later than an allowable time limit by generating a timing event observation (TEO) signal. The allowable time limit is defined by at least one triggering edge of at least one triggering signal coupled to the first register circuit (502). The system uses said TEO signal to trigger an increase in said operating voltage faster than said time constant.

Abstract: A Building Management System (BMS) may be controlled in accordance with predicted occupancy using a trained model. A model is trained by providing the model with time stamped environmental data and corresponding time stamped occupancy data pertaining to a training building, wherein the time stamped environmental data is derived from one or more environmental sensors of the training building and the corresponding time stamped occupancy data is derived from one or more occupancy sensors of the training building. Once trained, the trained model is provided with time stamped environmental data for a use building that is derived from one or more environmental sensors of the use building. Occupancy data for the use building is not required. The trained model outputs a predicted occupancy value that represents a predicted occupancy count in the use building, and the BMS of the use building is controlled based at least in part on the predicted occupancy value.

Abstract: Digital values obtained from an output of a preceding circuit element are temporarily stored and made available for a subsequent circuit element at a controlled moment of time. A digital value is received for temporary storage, as well as a triggering signal, a triggering edge of which defines an allowable time limit before which a digital value must appear at said data input to become available for said subsequent circuit element. A sequence of first and second pulse-enabled subregister stages is used to temporarily store said digital value. Said triggering signal is provided to said first pulse-enabled subregister stage delayed with respect to the triggering signal received by said second pulse-enabled subregister stage. The length of the delay is a fraction of a cycle of the triggering signal.

Abstract: An illustrative example embodiment of an electronic device includes an integrated circuit component having a plurality of solder balls on one side. The substrate includes a first side adjacent the one side of the integrated circuit component. The substrate includes a plurality of openings. At least some of those openings are aligned with the solder balls. A cooling plate is situated toward a second side of the substrate. A thermally conductive material within the plurality of openings is thermally coupled with the cooling plate. At least some of the thermally conductive material is thermally coupled with the solder balls. The cooling plate comprises the thermally conductive material and the thermally conductive material within the plurality of openings forms extensions from the cooling plate.

Abstract: A monitor circuit (301) for monitoring changes in an input digital value of a register circuit comprises a data input (302) configured to receive a copy of the input digital value of said register circuit, and one or more triggering signal inputs (303) configured to receive one or more triggering signals. One or more triggering edges thereof define an allowable time limit before which a digital value must appear at a data input of said register circuit to become properly stored in said register circuit. The monitor circuit comprises a data event (DE) output (305), so that said monitor circuit is configured to produce a DE signal at said DE output (305) in response to a digital value at said data input (302) changing within a time window defined by said one or more triggering signals.

Abstract: Thermal management and shielding techniques for a radar device of a vehicle, the radar device having a radar transceiver circuit and a radar-transmissive radome, include a housing formed of a thermally-conductive plastic material and configured to receive and provide shield grounding to the radar transceiver circuit, and a metal layer applied to an inner surface of the housing to provide for thermal spreading of heat energy generated by the radar transceiver circuit.

Abstract: An illustrative example embodiment of an electronic device includes an integrated circuit component having a plurality of solder balls on one side. The substrate includes a first side adjacent the one side of the integrated circuit component. The substrate includes a plurality of openings. At least some of those openings are aligned with the solder balls. A cooling plate is situated toward a second side of the substrate. A thermally conductive material within the plurality of openings is thermally coupled with the cooling plate. At least some of the thermally conductive material is thermally coupled with the solder balls.

Abstract: Microelectronic circuit com-prises a plurality of logic units and register circuits, arranged into a plu-rality of processing paths, and a plu-rality of monitoring units associated with respective ones of said processing paths. Each of said monitoring units is configured to produce an observation signal as a response to anomalous opera-tion of the respective processing path. Each of said plurality of logic units belongs to one of a plurality of delay classes according to an amount of delay that it is likely to generate. Said de-lay classes comprise first, second, and third classes, of which the first class covers logic units that are likely to generate longest delays, the second class covers logic units that are likely to generate shorter delays than said first class, and the third class covers logic units that are likely to generate shorter delays than said second class. At least some of said plurality of pro-cessing paths comprise logic units be-longing to said second class but are without monitoring units.

Abstract: A digital value obtained from a preceding circuit element is temporarily stored and made available for a subsequent circuit element at a controlled moment of time. The digital value is received through a data input. A triggering signal is also received, a triggering edge of which defines an allowable time limit before which a digital value must be available at said data input to become available for said subsequent circuit element. Between first and second pulse-enabled subregister stages, an internal digital value from the first pulse-enabled subregister stage and information of the changing moment of said digital value at the data input in relation to said allowable time limit are used to ensure passing a valid internal digital value to the second pulse-enabled subregister stage. Said second pulse-enabled subregister stage makes said valid internal digital value available for said subsequent circuit element.

Abstract: An illustrative example embodiment of an electronic device includes an integrated circuit component having a plurality of solder balls on one side. The substrate includes a first side adjacent the one side of the integrated circuit component. The substrate includes a plurality of openings. At least some of those openings are aligned with the solder balls. A cooling plate is situated toward a second side of the substrate. A thermally conductive material within the plurality of openings is thermally coupled with the cooling plate. At least some of the thermally conductive material is thermally coupled with the solder balls.

Abstract: In one aspect of the disclosure, a circuit includes an AFIFO in a first power domain coupled to a first data bus and configured to store up to N data words corresponding to N respective AFIFO outputs. A multiplexer (MUX) in the first power domain selectively coupled to the N AFIFO outputs may transfer, upon receiving a MUX input, less than N words onto a fixed interface. Read logic in a second power domain may send an asynchronous read pointer to the MUX input and may transfer the words output from the fixed interface to a second data bus. Write logic in the first power domain may send asynchronous write pointers to the AFIFO for tracking data writes thereto and to the read logic to determine values of the read pointer.

Abstract: The excitation of processing paths in a microelectronic circuit is organized by providing one or more pieces of input information to a decision-making software, and executing the decision-making software to decide, whether one or more of said processing paths of the microelectronic circuit are to be excited with test signals. Deciding that said processing paths are to be excited with said test signals results in proceeding to excite said one or more of said processing paths with said test signals and monitoring whether timing events occur on such one or more excited processing paths. A timing event is a change in a digital value at an input of a respective register circuit on an excited processing path, which change took place later than an allowable time limit defined by a triggering signal to said respective register circuit.

Abstract: An electromagnetic interference (EMI) shielding and thermal management system, method, and automotive radar system for an integrated circuit of a product circuit board (PCB) of a radar sensor includes a shield member disposed above the integrated circuit and extending to unpopulated areas of the PCB and configured to shield the integrated circuit from EMI and transfer heat energy generated by the integrated circuit away from the integrated circuit, and a set of pin members configured to be inserted through respective apertures defined by the shield member and the PCB and configured to transfer the heat energy from the shield member to an environment external to the PCB.

Abstract: A controllable voltage source (902) is coupled to a microelectronic circuit (901) for providing an operating voltage. Said microelectronic circuit (901) is adaptive, so its performance is at least partly configurable by value of said operating voltage. The operating voltage is regulated into conformity with a target value. Reregulating said operating voltage into conformity with a new target value involves a time constant. On a processing path a first register circuit (502) comprises a data input coupled to an output of a preceding first logic unit (501). The microelectronic circuit (901) responds to a digital value at said data input changing later than an allowable time limit by generating a timing event observation (TEO) signal. The allowable time limit is defined by at least one triggering edge of at least one triggering signal coupled to the first register circuit (502). The system uses said TEO signal to trigger an increase in said operating voltage faster than said time constant.

Abstract: A monitor circuit (301) for monitoring changes in an input digital value of a register circuit comprises a data input (302) configured to receive a copy of the input digital value of said register circuit, and one or more triggering signal inputs (303) configured to receive one or more triggering signals. One or more triggering edges thereof define an allowable time limit before which a digital value must appear at a data input of said register circuit to become properly stored in said register circuit. The monitor circuit comprises a data event (DE) output (305), so that said monitor circuit is configured to produce a DE signal at said DE output (305) in response to a digital value at said data input (302) changing within a time window defined by said one or more triggering signals.

Abstract: Microelectronic circuit com-prises a plurality of logic units and register circuits, arranged into a plu-rality of processing paths, and a plu-rality of monitoring units associated with respective ones of said processing paths. Each of said monitoring units is configured to produce an observation signal as a response to anomalous opera-tion of the respective processing path. Each of said plurality of logic units belongs to one of a plurality of delay classes according to an amount of delay that it is likely to generate. Said de-lay classes comprise first, second, and third classes, of which the first class covers logic units that are likely to generate longest delays, the second class covers logic units that are likely to generate shorter delays than said first class, and the third class covers logic units that are likely to generate shorter delays than said second class. At least some of said plurality of pro-cessing paths comprise logic units be-longing to said second class but are without monitoring units.

Abstract: A microelectronic circuit comprises a plurality of logic units and register circuits arranged into a plurality of processing paths. At least one monitor circuit (404) is associated with a first register circuit (301), said monitor circuit (404) being configured to produce a timing event observation signal as a response to a change in a digital value at an input (D) of the first register circuit (301) that took place later than an allowable time limit defined by a triggering signal (CP) to said first register circuit (301). A first processing path goes through a first logic unit (501) to said first register circuit (301) and is a delay critical processing path due to an amount of delay that it is likely to generate. The microelectronic circuit comprises a controllable data event injection point (503) for controllably generating a change of a digital value propagating to said first logic unit (501) irrespective of what other data is processed on said first processing path.

Abstract: The performance of a microelectronic circuit can be configured by making an operating parameter assume an operating parameter value. An operating method comprises selectively setting the microelectronic circuit into a test mode that differs from a normal operating mode of the microelectronic circuit, and utilizing said test mode to input test input signals consisting of test input values into one or more adaptive processing paths within the microelectronic circuit. An adaptive processing path comprises processing logic and register circuits configured to produce output values from input values input to them. The performance of such an adaptive processing path can be configured by making an operating parameter assume an operating parameter value.

Abstract: Digital values obtained from an output of a preceding circuit element are temporarily stored and made available for a subsequent circuit element at a controlled moment of time. A digital value is received for temporary storage, as well as a triggering signal, a triggering edge of which defines an allowable time limit before which a digital value must appear at said data input to become available for said subsequent circuit element. A sequence of first and second pulse-enabled subregister stages is used to temporarily store said digital value. Said triggering signal is provided to said first pulse-enabled subregister stage delayed with respect to the triggering signal received by said second pulse-enabled subregister stage. The length of the delay is a fraction of a cycle of the triggering signal.

Abstract: A digital value obtained from a preceding circuit element is temporarily stored and made available for a subsequent circuit element at a controlled moment of time. The digital value is received through a data input. A triggering signal is also received, a triggering edge of which defines an allowable time limit before which a digital value must be available at said data input to become available for said subsequent circuit element. Between first and second pulse-enabled subregister stages, an internal digital value from the first pulse-enabled subregister stage and information of the changing moment of said digital value at the data input in relation to said allowable time limit are used to ensure passing a valid internal digital value to the second pulse-enabled subregister stage. Said second pulse-enabled subregister stage makes said valid internal digital value available for said subsequent circuit element.