Abstract: A defect management system is disclosed for disc storage systems which avoids the access latency associated with conventional linear replacement techniques by dispersing spare segments throughout each track at a regular interval and buffering sectors inbetween a defective sector and the corresponding spare segment during read and write operations. In one embodiment, a spare segment is an entire sector which replaces a defective data sector; and in an alternative embodiment, a spare segment stores only the defective portion of a data sector which is more efficient, but also more complicated in implementation. In both embodiments, the defect management system comprises a defect locator for locating a defective segment within a data sector. Once located, the defect management system maps the defective sector (or the defective portion thereof) to the nearest available spare segment.

Abstract: An apparatus and method of generating redundancy symbols and syndromes which is order-programmable is disclosed. The apparatus and method involves the implementation of an error correcting encoder/decoder for polynomial codes which uses a single circuit to generate check symbols during the transmit operation and to generate syndromes during a receive operation. The selection of roots for the code generator, and hence, the code order is programmable.

Abstract: A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL(1,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, together with the error-tolerant sync mark detection and the ability to recover data when the sync mark is obliterated, allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery.

Abstract: A measurement circuit is provided to obtain data for monitoring the quality of performance from a digital read channel. Elements of the digital read channel including a sequence detector are incorporated into an integrated circuit together with the measurement circuit. The measurement circuit relates digitized samples of readback data from a magnetic storage device to surrounding samples so that particular samples can be collected in accordance with their surroundings. The circuit includes a programmable time window which can be repeatedly opened for data collection. The circuit is designed to collect various types of data including the bit error rate, sample value, squared sample error, squared gain error, squared timing error, and the occurrences of sample error when it is outside an acceptable programmable threshold. The measurement circuit includes a signal generator for producing a test pattern that is first stored and then read to produce the digitized readback sample values.

Abstract: A disc drive storage system is disclosed that employs sector level and track level error correction systems (ECS), wherein the track level error correction capability is increased by interleaving the track level redundancy. In the preferred embodiment, each sector on the disc is divided into three interleaves or codewords with sector level redundancy generated for each interleaved codeword. The track level redundancy is then generated by combining the interleaved codewords separately according to a predetermined error correction operation (e.g., byte XOR) to form an interleaved redundancy sector. During readback, the sector level ECS generates an erasure pointer corresponding to an uncorrectable codeword within a sector for use by the track level ECS. In this manner, the track level ECS can correct up to three uncorrectable sectors when three sectors contain a single uncorrectable codeword in separate interleaves.

Abstract: In a disc drive storage system employing a track level redundancy sector for reconstructing a data sector unrecoverable at the sector level, the latency of the storage system is minimized by performing a write operation according to the following steps:1. seek to the target track corresponding to the sector(s) to be written;2. once at the target track, wait for the recording head to reach the first sector in the track (sector 0);3. begin reading and processing the sectors in the target track to regenerate the redundancy sector;4. when the recording head reaches the target sector(s), combine the new data sector(s) with the regenerated redundancy sector, switch to a write operation, and write the new sectors to the track;5. after writing the new data sectors to the track, switch back to a read operation and continue reading the data sectors in the track and combining them with the regenerated redundancy sector; and6.

Abstract: A k-bit serial finite field multiplier circuit for multiplying a predetermined number of elements Wj in a finite field GF(2.sup.m) by a respective predetermined constant and summing the resulting products. The bits of the elements Wj are loaded serially, low order first, into the bit serial multiplier. For k greater than 1, the bits of the elements Wj are divided into k interleaves and processed by the multiplier k bits at a time. The multiplier comprises k number of linear feedback shift registers for performing the multiplication such that after m/k clock cycles the content of the shift registers is the sum of the products:Y=C1*W1+C2*W2+. . . Cj*Wj.

Abstract: Apparatus and methods are disclosed for providing an improved system for encoding and decoding of Reed-Solomon and related codes. The system employs a k-bit-serial shift register for encoding and residue generation. For decoding, a residue is generated as data is read. Single-burst errors are corrected in real time by a k-bit-serial burst trapping decoder that operates on this residue. Error cases greater than a single burst are corrected with a non-real-time firmware decoder, which retrieves the residue and converts it to a remainder, then converts the remainder to syndromes, and then attempts to compute error locations and values from the syndromes. In the preferred embodiment, a new low-order first, k-bit-serial, finite-field constant multiplier is employed within the burst trapping circuit. Also, code symbol sizes are supported that need not equal the information byte size. The implementor of the methods disclosed may choose time-efficient or space-efficient firmware for multiple-burst correction.

Abstract: A filter for compensating discrete secondary pulse formations associated with a data stream of discrete main pulses produced from data read from magnetic media. The filter's impulse response comprises a center coefficient with side compensating coefficients for attenuating the secondary pulses when the input signal is convolved with the impulse response. The magnitude and delay of the compensation coefficients are programmable and are adaptively adjusted to optimize the impulse response for a given environment. In a traditional FIR embodiment, two delay lines are used to generate the two programmable delays between the center coefficient and side compensation coefficients. In the preferred embodiment, an IIR filter provides the two programmable delays using only one delay line thereby reducing the size and cost of the circuit. Also in the preferred embodiment, the data stream is interleaved into an even and odd data stream and processed in parallel by two filters in order to double the throughput.

Abstract: Signal processing circuitry receives input signals representing modulation encoded binary data signals. The signal processing circuitry contains a plurality of signal quality detectors which monitor a corresponding plurality of different characteristics of each received signal to determine whether or not the signal is of an adequate quality insofar as concerns the characteristic of the signal associated with each detector. Each detector generates a binary output signal representing a confidence level pointer associated with each such received signal. The pointer signals are stored in a buffer with received data signals. The contents of the buffer, which at this time contain the bytes of the received data record as well as the associated pointer bytes, are made available to a control module.

Abstract: An error correction system (1000) included in a utilization device (1002) operates upon a plurality of sectors (S) stored in a data buffer (1100) for performing write-from-host and read-from-device operations. Overlapping and asynchronous operational steps are performed with respect to the plurality of sectors, the operational steps including sector transfer into buffer, sector correction, and sector transfer out of buffer. The error correction system (1000) includes a plurality of subsystems which are supervised and sequenced by correction controller (1020). The subsystems include a CRC generation and checking subsystem (1030); an LBA subsystem (1040); an ECC/Syndrome Generator subsystem (1050); a header (ID) subsystem (1060); a correction subsystem (1070); and, a correction checker system (1075).

Abstract: An apparatus and method of generating redundancy symbols and syndromes which is order-programmable is disclosed. The apparatus and method involves the implementation of an error correcting encoder/decoder for polynomial codes which uses a single circuit to generate check symbols during the transmit operation and to generate syndromes during a receive operation. The selection of roots for the code generator, and hence, the code order is programmable.

Abstract: A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL(1,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, together with the error-tolerant sync mark detection and the ability to recover data when the sync mark is obliterated, allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery.

Abstract: A general-purpose, single-pass, adaptive, and lossless data compression invention implements an LZ1-like method using a hash-based architecture. It is suitable for use in data storage and data communications applications. Implementation efficiency, in terms of required memory and logic gates relative to the typical compression ratio achieved, is highly optimized. An easy-to-implement and quick-to-verify hash function is used. Differential copy lengths may be used to reduce the number of bits required to encode the copy-length field within copy tokens. That is, if multiple matches to a sequence of input bytes are found in the current window, then the length of the copy may be encoded as the difference between the lengths of the longest and the second-longest match, which results in a smaller copy length which likely has a shorter encoded representation.

Abstract: Apparatus and methods are disclosed for providing an improved system for identifying the location and value of errors introduced in binary data encoded using Reed-Solomon and related codes and to detect miscorrections of such codes with an auxiliary code. The invention employs an architecture based on a microcode engine that is specialized for error identification and that supports interleaved codewords. This architecture can be efficiently fabricated as an integrated circuit, yet is capable of identifying multiple introduced errors "on the fly" i.e. with performance sufficient to not significantly slow the process of reading from data storage or transmission subsystems such as, but not limited to, optical disks. In the preferred embodiment, a new two-step method of error syndrome computation is employed to reduce circuit cost and complexity. An improved iterative algorithm is provided which reduces circuit cost and complexity and decreases the time required to generate the error locator polynomial.

Abstract: A timing circuit having an analog to digital converter to sample an analog signal, a controlled oscillator for controlling sample times of the analog to digital converter, a circuit to detect pulses in the analog signal, a phase error circuit to subtract one of two samples from the other to create a phase error measurement and a frequency error circuit to add two samples together to create a frequency error measurement. The two samples are taken from either side of a pulse. The phase error measurement is used by the controlled oscillator to adjust the sample timing to take samples at desired locations on the pulse. The circuit also contains constant values used to compensate for the pulse being asymmetrical and to compensate for other pulses that occur close to the detected pulse. The circuit also inserts a known frequency in place of the analog signal to establish a frequency of the controlled oscillator.

Abstract: Disclosed is a pulse detector that uses four samples of an analog signal to detect a pulse as soon as one sample beyond the time of the peak of the signal level at the pulse. The pulse detector can detect pulses by sampling at the center of a peak of the pulse or by sampling at either side of the peak of the pulse. The pulse detector detects pulses while tracking data, and it uses an alternate detection system for detecting pulses while acquiring timing and gain lock on a signal having a known data pattern. The detector uses either the sampled signal levels directly, or a moving average of two samples to perform the detection.

Abstract: A mixed analog and digital gain control circuit for controlling the amplitude of an analog input signal. The circuit has a variable gain amplifier that receives the signal from a read/write recording head preamplifier. The output of the variable gain amplifier is connected through a multiplexer and equalizer to an analog to digital converter for converting the analog signal to digital sample values at controlled sampling times. A gain control circuit receives the digital values and the output of a pulse detector indicating when a pulse has occurred. A gain error detector within the gain control circuit determines the amount of error in the amplitude of each detected pulse, and this error amount is filtered and sent through a digital to analog converter and then through an exponentiating circuit. The output of the exponentiating circuit is connected to a gain control input of the variable gain amplifier.

Abstract: A Viterbi detector is modified to reduce its implementation complexity. A partial-response signal may be viewed as a sequence of expected samples generated from a finite-state-machine model. In a typical Viterbi demodulator implemented using the add, compare, select (ACS) method, each state in the expected sample sequence model is associated with a hardware module to perform the functions of adding new branch error metrics to path error metrics, comparing path error metrics, and selecting the path having the lowest path error metric. In this invention, an ACS module may have two or more sequence-model states dynamically associated with it, such that at some times one sequence-model state is associated with it and at other times another sequence-model state is associated with it. This reduces the number of ACS modules required and also reduces the size/complexity of the demodulator's path memories which must store one path for each ACS module.

Abstract: Apparatus and methods are disclosed for providing an improved system for encoding and decoding of Reed-Solomon and related codes. The system employs a k-bit-serial shift register for encoding and residue generation. For decoding, a residue is generated as data is read. Single-burst errors are corrected in real time by a k-bit-serial burst trapping decoder that operates on this residue. Error cases greater than a single burst are corrected with a non-real-time firmware decoder, which retrieves the residue and converts it to a remainder, then converts the remainder to syndromes, and then attempts to compute error locations and values from the syndromes. In the preferred embodiment, a new low-order first, k-bit-serial, finite field constant multiplier is employed within the burst trapping circuit. Also, code symbol sizes are supported that need not equal the information byte size. The implementor of the methods disclosed may choose time-efficient or space-efficient firmware for multiple-burst correction.