Abstract: The low-data-delay triple-coverage code for on-the-fly error correction apparatus allows on-the-fly error correction with fewer redundancy bytes than needed for a non-overlaid data redundancy structure thereby producing corrected data with a low data delay. The present apparatus divides a received block of data into a plurality of fixed size sub-blocks with the last sub-block size being smaller than or equal to the fixed sub-block size. Three predefined error correcting code generator polynomials are used to accumulate redundancy values for the sub-blocks. At the end of each sub-block one of the three pre-defined error correcting code generator polynomials will have accumulated a redundancy value across the present sub-block data and the previous two sub-blocks of data and redundancy. After the accumulated redundancy has been output as write data the predefined error correcting code generator polynomial is reset.

Abstract: A Loss of Lock Detector and Re-lock Control function using digital techniques to detect a programmable difference in frequencies over a programmable range. Once Loss of Lock is detected, the Re-lock sequence is initiated and PLLIS, PLLMS & PLLGS are stepped through a programmable sequence. The invention detects the frequency difference by counting down two counters and evaluating the value left in one when the other reaches terminal count using a programmable tolerance of frequency differences before Loss of Lock is declared. The complexity and cost of implementation of the invention is reduced by multiple use of a single down counter. Other features of the invention are disclosed.

Abstract: Apparatus and methods are disclosed for providing fast decoding of Reed-Solomon and related codes. Cases of one and two data symbol errors are decoded directly from the remainder using a large pre-computed table without calculating syndromes. Techniques for decoding cases of more than two errors are given where an optimized Chien search is used when more than four errors remain; when four or fewer errors remain, the Chien search is eliminated in favor of locating an error by direct solution of the error locator polynomial. The error locator and syndrome polynomials are adjusted after each error is found, and the error evaluator polynomial need not be computed.

Abstract: Disclosed is a serial encoder and time domain syndrome generator circuit utilized in a Reed-Solomon code application where the code has been defined with the conventional or standard representation of a finite field. The encoder will process k bits of an m-bit symbol per clock cycle, where 1.ltoreq.k.ltoreq.m and k evenly divides m. The encoder will process data in an interleave mode wherein data symbols of multiple codewords are interleaved in an interleaved data block. The encoder allows pipeline processing of register data within the encoder and time domain syndrome generator circuit to minimize circuit delay, and a linear network within the encoder is reduced in complexity by selecting a self-reciprocal code generator polynomial.

Abstract: Apparatus is disclosed for providing an improved encoder and frequency-domain syndrome generator circuit implementing Reed-Solomon codes which reduces hardware by sharing circuitry between the encoding and frequency-domain syndrome generation functions. Self-checking for proper encoder operation during write operations is achieved by verifying that all remainders from dividing codewords by factors of the code generator polynomial are equal to zero after encoding. Apparatus implements fast finite-field multiplication by a selected constant using Read Only Memory circuits. Hardware required is further reduced by incorporating Random Access Memory circuits and employing time-multiplexing techniques. Interleaved codewords are supported by implementing memory circuits for storing intermediate results of other codewords while processing symbols from one codeword.

Abstract: The present invention provides methods and apparatus for improved error detection in a data processing system. The techniques of the present invention insure that there is a high probability that an error in a record of data (each record comprising a plurality of data bits) is detected. In the event of an error, the present invention applies a randomizing function to the error which modifies subsequent bits within the record and then propagates and further randomizes the error throughout the record to magnify its apparent size. The randomizing and propagation of the error significantly lowers the misdetection probability for random errors within a record, in that error detectability is no longer pattern sensitive. The use of both propagation and randomization functions significantly alters the data containing an error, such that a high probability of detection using check-sum techniques exists.

Abstract: Data for recordation on a video disc is given multi-redundancy at block, field and group levels. Raw data is filled typically serially row by indexed row of 8-bit words with at least one and preferably 3 words being auxiliary check words derived from the remainder of the data field of the block. Block filling is completed with the addition of preferred Reed/Solomon error-correction redundancy filling two rows for column error detection and correction and two columns for row error detection and correction. Thirty blocks, so prepared, are processed to obtain two redundant blocks, completing a 32-block data field. Writing the data onto the video disc occurs with a three-dimensional diagonal interleave at the field level. After interleave each field is additionally XORd with 62 other fields to create a redundant field. This redundant field plus the 63 data fields comprise a group. The group of fields is written to the video disk so as to maximally spatially separate adjacent fields.

Abstract: A shared encoder/decoder circuit for use with a Reed-Solomon coding scheme of an optical disk storage system. The optical disk system includes a drive adapted to permanently store data on a removable platter. Prior to recording a data byte on the platter, the data is encoded with a Reed-Solomon code. When the data is read from the disk, it is decoded and error correction syndromes are generated. The same circuitry is shared for performing the encoding and decoding functions. This circuitry includes independent sets of a RAM, coupled to one input of an exclusive OR (modulo two sum) adding circuit. The output of the adding circuit is fed back to an input to the RAM. Two multiplier circuits are coupled to the output of the RAM. A product of one is tied to one input of the modulo two addition circuit.