Patents by Inventor Neil Greeley
Neil Greeley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8865544Abstract: Some embodiments include a method of forming a capacitor. An opening is formed through a silicon-containing mass to a base, and sidewalls of the opening are lined with protective material. A first capacitor electrode is formed within the opening and has sidewalls along the protective material. At least some of the silicon-containing mass is removed with an etch. The protective material protects the first capacitor electrode from being removed by the etch. A second capacitor electrode is formed along the sidewalls of the first capacitor electrode, and is spaced from the first capacitor electrode by capacitor dielectric. Some embodiments include multi-material structures having one or more of aluminum nitride, molybdenum nitride, niobium nitride, niobium oxide, silicon dioxide, tantalum nitride and tantalum oxide. Some embodiments include semiconductor constructions.Type: GrantFiled: July 11, 2012Date of Patent: October 21, 2014Assignee: Micron Technology, Inc.Inventors: Joseph Neil Greeley, Duane M. Goodner, Vishwanath Bhat, Vassil N. Antonov, Prashant Raghu
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Patent number: 8853682Abstract: Self-aligning fabrication methods for forming memory access devices comprising a doped chalcogenide material. The methods may be used for forming three-dimensionally stacked cross point memory arrays. The method includes forming an insulating material over a first conductive electrode, patterning the insulating material to form vias that expose portions of the first conductive electrode, forming a memory access device within the vias of the insulating material and forming a memory element over the memory access device, wherein data stored in the memory element is accessible via the memory access device. The memory access device is formed of a doped chalcogenide material and formed using a self-aligned fabrication method.Type: GrantFiled: February 20, 2014Date of Patent: October 7, 2014Assignee: Micron Technology, Inc.Inventors: Neil Greeley, Gurtej Sandhu, John Smythe, Bhaskar Srinivasan
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Publication number: 20140225028Abstract: Methods for preventing isotropic removal of materials at corners faulted by seams, keyholes, and other anomalies in films or other structures include use of etch blockers to cover or coat such corners. This covering or coating prevents exposure of the corners to isotropic etch solutions and cleaning solutions and, thus, prevents higher material removal rates at the corners than at smoother areas of the structure or film. Solutions, including wet etchants and cleaning solutions, that include at least one type of etch blocker are also disclosed, as are systems for preventing higher rates of material removal at corners formed by seams, crevices, or recesses in a film or other structure. Semiconductor device structures in which etch blockers are located so as to prevent isotropic etchants from removing material from corners of seams, crevices, or recesses of a film or other structure at undesirably high rates are also disclosed.Type: ApplicationFiled: April 15, 2014Publication date: August 14, 2014Applicant: Micron Technology, Inc.Inventors: Nishant Sinha, J. Neil Greeley
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Publication number: 20140166972Abstract: Self-aligning fabrication methods for forming memory access devices comprising a doped chalcogenide material. The methods may be used for forming three-dimensionally stacked cross point memory arrays. The method includes forming an insulating material over a first conductive electrode, patterning the insulating material to form vias that expose portions of the first conductive electrode, forming a memory access device within the vias of the insulating material and forming a memory element over the memory access device, wherein data stored in the memory element is accessible via the memory access device. The memory access device is formed of a doped chalcogenide material and formed using a self-aligned fabrication method.Type: ApplicationFiled: February 20, 2014Publication date: June 19, 2014Applicant: MICRON TECHNOLOGY, INC.Inventors: Neil Greeley, Gurtej Sandhu, John Smythe, Bhaskar Srinivasan
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Publication number: 20140151843Abstract: Methods of forming metal oxide structures and methods of forming metal oxide patterns on a substrate using a block copolymer system formulated for self-assembly. A block copolymer at least within a trench in the substrate and including at least one soluble block and at least one insoluble block may be annealed to form a self-assembled pattern including a plurality of repeating units of the at least one soluble block laterally aligned with the trench and positioned within a matrix of the at least one insoluble block. The self-assembled pattern may be exposed to a metal oxide precursor that impregnates the at least one soluble block. The metal oxide precursor may be oxidized to form a metal oxide. The self-assembled pattern may be removed to form a pattern of metal oxide lines on the substrate surface. Semiconductor device structures are also described.Type: ApplicationFiled: February 10, 2014Publication date: June 5, 2014Applicant: Micron Technology, Inc.Inventors: Dan B. Millward, Timothy A. Quick, J. Neil Greeley
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Patent number: 8729002Abstract: Methods for preventing isotropic removal of materials at corners formed by seams, keyholes, and other anomalies in films or other structures include use of etch blockers to cover or coat such corners. This covering or coating prevents exposure of the corners to isotropic etch solutions and cleaning solutions and, thus, prevents higher material removal rates at the corners than at smoother areas of the structure or film. Solutions, including wet etchants and cleaning solutions, that include at least one type of etch blocker are also disclosed, as are systems for preventing higher rates of material removal at corners formed by seams, crevices, or recesses in a film or other structure. Semiconductor device structures in which etch blockers are located so as to prevent isotropic etchants from removing material from corners of seams, crevices, or recesses of a film or other structure at undesirably high rates are also disclosed.Type: GrantFiled: March 6, 2012Date of Patent: May 20, 2014Assignee: Micron Technology, Inc.Inventors: Nishant Sinha, J. Neil Greeley
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Patent number: 8686411Abstract: Self-aligning fabrication methods for forming memory access devices comprising a doped chalcogenide material. The methods may be used for forming three-dimensionally stacked cross point memory arrays. The method includes forming an insulating material over a first conductive electrode, patterning the insulating material to form vias that expose portions of the first conductive electrode, forming a memory access device within the vias of the insulating material and forming a memory element over the memory access device, wherein data stored in the memory element is accessible via the memory access device. The memory access device is formed of a doped chalcogenide material and formed using a self-aligned fabrication method.Type: GrantFiled: March 15, 2013Date of Patent: April 1, 2014Assignee: Micron Technology, Inc.Inventors: Neil Greeley, Bhaskar Srinivasan, Gurtej Sandhu, John Smythe
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Patent number: 8669645Abstract: Methods of forming metal oxide structures and methods of forming metal oxide patterns on a substrate using a block copolymer system formulated for self-assembly. A block copolymer at least within a trench in the substrate and including at least one soluble block and at least one insoluble block may be annealed to form a self-assembled pattern including a plurality of repeating units of the at least one soluble block laterally aligned with the trench and positioned within a matrix of the at least one insoluble block. The self-assembled pattern may be exposed to a metal oxide precursor that impregnates the at least one soluble block. The metal oxide precursor may be oxidized to form a metal oxide. The self-assembled pattern may be removed to form a pattern of metal oxide lines on the substrate surface. Semiconductor device structures are also described.Type: GrantFiled: December 22, 2011Date of Patent: March 11, 2014Assignee: Micron Technology, Inc.Inventors: Dan B. Millward, Timothy A. Quick, J. Neil Greeley
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Publication number: 20140015097Abstract: Some embodiments include a method of forming a capacitor. An opening is formed through a silicon-containing mass to a base, and sidewalls of the opening are lined with protective material. A first capacitor electrode is formed within the opening and has sidewalls along the protective material. At least some of the silicon-containing mass is removed with an etch. The protective material protects the first capacitor electrode from being removed by the etch. A second capacitor electrode is formed along the sidewalls of the first capacitor electrode, and is spaced from the first capacitor electrode by capacitor dielectric. Some embodiments include multi-material structures having one or more of aluminum nitride, molybdenum nitride, niobium nitride, niobium oxide, silicon dioxide, tantalum nitride and tantalum oxide. Some embodiments include semiconductor constructions.Type: ApplicationFiled: July 11, 2012Publication date: January 16, 2014Applicant: MICRON TECHNOLOGY, INC.Inventors: Joseph Neil Greeley, Duane M. Goodner, Vishwanath Bhat, Vassil N. Antonov, Prashant Raghu
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Publication number: 20130234091Abstract: Self-aligning fabrication methods for forming memory access devices comprising a doped chalcogenide material. The methods may be used for forming three-dimensionally stacked cross point memory arrays. The method includes forming an insulating material over a first conductive electrode, patterning the insulating material to form vias that expose portions of the first conductive electrode, forming a memory access device within the vias of the insulating material and forming a memory element over the memory access device, wherein data stored in the memory element is accessible via the memory access device. The memory access device is formed of a doped chalcogenide material and formed using a self-aligned fabrication method.Type: ApplicationFiled: March 15, 2013Publication date: September 12, 2013Applicant: MICRON TECHNOLOGY, INC.Inventors: Neil Greeley, Bhaskar Srinivasan, Gurtej Sandhu, John Smythe
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Patent number: 8513135Abstract: Methods for reducing line roughness of spacers and other features utilizing a non-plasma and non-wet etch fluoride processing technology are provided. Embodiments of the methods can be used for spacer or line reduction and/or smoothing the surfaces along the edges of such features through the reaction and subsequent removal of material.Type: GrantFiled: September 27, 2011Date of Patent: August 20, 2013Assignee: Micron Technology, Inc.Inventors: Joseph Neil Greeley, Paul Morgan, Mark Kiehlbauch
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Publication number: 20130164902Abstract: A method of forming capacitors includes forming support material over a substrate. A first capacitor electrode is formed within individual openings in the support material. A first etching is conducted only partially into the support material using a liquid etching fluid to expose an elevationally outer portion of sidewalls of individual of the first capacitor electrodes. A second etching is conducted into the support material using a dry etching fluid to expose an elevationally inner portion of the sidewalls of the individual first capacitor electrodes. A capacitor dielectric is formed over the outer and inner portions of the sidewalls of the first capacitor electrodes. A second capacitor electrode is formed over the capacitor dielectric.Type: ApplicationFiled: December 21, 2011Publication date: June 27, 2013Applicant: Micron Technology, Inc.Inventors: Joseph Neil Greeley, Prashant Raghu, Niraj B. Rana
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Patent number: 8461060Abstract: A semiconductor device and a method of forming it are disclosed in which at least two adjacent conductors have an air-gap insulator between them which is covered by nanoparticles of insulating material being a size which prevent the nanoparticles from substantially entering into the air-gap.Type: GrantFiled: September 14, 2012Date of Patent: June 11, 2013Assignee: Micron Technology, Inc.Inventors: Nishant Sinha, Gurtej Sandhu, Neil Greeley, John Smythe
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Patent number: 8415661Abstract: Self-aligning fabrication methods for forming memory access devices comprising a doped chalcogenide material. The methods may be used for forming three-dimensionally stacked cross point memory arrays. The method includes forming an insulating material over a first conductive electrode, patterning the insulating material to form vias that expose portions of the first conductive electrode, forming a memory access device within the vias of the insulating material and forming a memory element over the memory access device, wherein data stored in the memory element is accessible via the memory access device. The memory access device is formed of a doped chalcogenide material and formed using a self-aligned fabrication method.Type: GrantFiled: June 7, 2012Date of Patent: April 9, 2013Assignee: Micron Technology, Inc.Inventors: Neil Greeley, Bhaskar Srinivasan, Gurtej Sandhu, John Smythe
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Publication number: 20130005143Abstract: A semiconductor device and a method of forming it are disclosed in which at least two adjacent conductors have an air-gap insulator between them which is covered by nanoparticles of insulating material being a size which prevent the nanoparticles from substantially entering into the air-gap.Type: ApplicationFiled: September 14, 2012Publication date: January 3, 2013Inventors: Nishant Sinha, Gurtej Sandhu, Neil Greeley, John Smythe
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Publication number: 20120309999Abstract: A method of removing at least a portion of a silicon oxide material is disclosed. The silicon oxide is removed by exposing a semiconductor structure comprising a substrate and the silicon oxide to an ammonium fluoride chemical treatment and a subsequent plasma treatment, both of which may be effected in the same vacuum chamber of a processing apparatus. The ammonium fluoride chemical treatment converts the silicon oxide to a solid reaction product in a self-limiting reaction, the solid reaction product then being volatilized by the plasma treatment. The plasma treatment includes a plasma having an ion bombardment energy of less than or equal to approximately 20 eV. An ammonium fluoride chemical treatment including an alkylated ammonia derivative and hydrogen fluoride is also disclosed.Type: ApplicationFiled: August 9, 2012Publication date: December 6, 2012Applicant: MICRON TECHNOLOGY, INC.Inventors: Mark W. Kiehlbauch, J. Neil Greeley, Paul A. Morgan
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Patent number: 8298964Abstract: A semiconductor device and a method of forming it are disclosed in which at least two adjacent conductors have an air-gap insulator between them which is covered by nanoparticles of insulating material being a size which prevent the nanoparticles from substantially entering into the air-gap.Type: GrantFiled: April 28, 2011Date of Patent: October 30, 2012Assignee: Micron Technology, Inc.Inventors: Nishant Sinha, Gurtej Sandhu, Neil Greeley, John Smythe
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Publication number: 20120241911Abstract: Self-aligning fabrication methods for forming memory access devices comprising a doped chalcogenide material. The methods may be used for forming three-dimensionally stacked cross point memory arrays. The method includes forming an insulating material over a first conductive electrode, patterning the insulating material to form vias that expose portions of the first conductive electrode, forming a memory access device within the vias of the insulating material and forming a memory element over the memory access device, wherein data stored in the memory element is accessible via the memory access device. The memory access device is formed of a doped chalcogenide material and formed using a self-aligned fabrication method.Type: ApplicationFiled: June 7, 2012Publication date: September 27, 2012Inventors: Neil Greeley, Bhaskar Srinivasan, Gurtej Sandhu, John Smythe
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Patent number: 8252194Abstract: A method of removing at least a portion of a silicon oxide material is disclosed. The silicon oxide is removed by exposing a semiconductor structure comprising a substrate and the silicon oxide to an ammonium fluoride chemical treatment and a subsequent plasma treatment, both of which may be effected in the same vacuum chamber of a processing apparatus. The ammonium fluoride chemical treatment converts the silicon oxide to a solid reaction product in a self-limiting reaction, the solid reaction product then being volatilized by the plasma treatment. The plasma treatment includes a plasma having an ion bombardment energy of less than or equal to approximately 20 eV. An ammonium fluoride chemical treatment including an alkylated ammonia derivative and hydrogen fluoride is also disclosed.Type: GrantFiled: May 2, 2008Date of Patent: August 28, 2012Assignee: Micron Technology, Inc.Inventors: Mark W. Kiehlbauch, J. Neil Greeley, Paul A. Morgan
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Publication number: 20120187335Abstract: Methods for preventing isotropic removal of materials at corners formed by seams, keyholes, and other anomalies in films or other structures include use of etch blockers to cover or coat such corners. This covering or coating prevents exposure of the corners to isotropic etch solutions and cleaning solutions and, thus, prevents higher material removal rates at the corners than at smoother areas of the structure or film. Solutions, including wet etchants and cleaning solutions, that include at least one type of etch blocker are also disclosed, as are systems for preventing higher rates of material removal at corners formed by seams, crevices, or recesses in a film or other structure. Semiconductor device structures in which etch blockers are located so as to prevent isotropic etchants from removing material from corners of seams, crevices, or recesses in a surface of a film or other structure at undesirably high rates are also disclosed.Type: ApplicationFiled: March 6, 2012Publication date: July 26, 2012Applicant: MICRON TECHNOLOGY, INC.Inventors: Nishant Sinha, J. Neil Greeley