Patents by Inventor Neng-Jye Yang
Neng-Jye Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11942362Abstract: Embodiments described herein relate generally to methods for forming a conductive feature in a dielectric layer in semiconductor processing and structures formed thereby. In some embodiments, a structure includes a dielectric layer over a substrate, a surface modification layer, and a conductive feature. The dielectric layer has a sidewall. The surface modification layer is along the sidewall, and the surface modification layer includes phosphorous and carbon. The conductive feature is along the surface modification layer.Type: GrantFiled: March 6, 2023Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jian-Jou Lian, Kuo-Bin Huang, Neng-Jye Yang, Li-Min Chen
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Patent number: 11923199Abstract: Aspects of the disclosure provide a method. The method includes forming a structure over a substrate, and forming a spacer layer on the structure, wherein the spacer layer has a recess. The method includes forming a mask layer over the spacer layer and in the recess, the mask layer including a first layer, a second layer and a third layer. The method includes patterning the third layer of the mask layer, and etching the first layer and the second layer of the mask layer to form an opening to expose the recess of the spacer layer, wherein the opening in the second layer has a first width; and. The method includes removing the second layer using a wet etchant, wherein the opening in the third layer has a second width, and the second with is greater than the first width.Type: GrantFiled: June 21, 2022Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Nai-Chia Chen, Wan Hsuan Hsu, Chia-Wei Wu, Neng-Jye Yang, Chun-Li Chou
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Publication number: 20240071820Abstract: An interconnect structure, which may be used for example in a semiconductor device, is disclosed. The interconnect structure includes a contact layer made of a metal; one or more dielectric layers on the contact layer, and a deposited layer made of an insulating material. The interconnect structure further includes a trench through the one or more dielectric layers so that a sidewall surface of the trench is formed by the one or more dielectric layers and a bottom surface of the trench is formed by a portion of the contact layer. The deposited layer is in the trench and a thickness of the insulating material on the sidewall surface of the trench is at least 2.1 times greater than a thickness of the insulating material on the bottom surface of the trench.Type: ApplicationFiled: August 24, 2022Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: Yu-Shan Yeh, Neng-Jye Yang, Kuo-Bin Huang
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Publication number: 20240021431Abstract: An apparatus, semiconductor device and method of manufacture are presented, wherein a hard mask layer and one or more etch stop layers are etched in an etching chamber. In an embodiment the semiconductor device is placed on a mounting platform at a first height and an etch process is performed, then the semiconductor device is moved to a second height within the chamber and a second etch process is performed, with the rotational speed of the semiconductor device reduced during movements in order to reduce the chance of cross contamination.Type: ApplicationFiled: July 28, 2023Publication date: January 18, 2024Inventors: Wan Hsuan Hsu, Jao Sheng Huang, Yen-Chiu Kuo, Yu-Li Cheng, Ya Tzu Chen, Neng-Jye Yang, Chun-Li Chou
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Publication number: 20230411210Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises an interlayer dielectric (ILD) layer disposed over a substrate; a first conductive feature at least partially embedded in the ILD layer; a dielectric layer disposed over and aligned with the ILD layer, wherein a top surface of the dielectric layer is above a top surface of the first conductive feature; an etch stop layer (ESL) disposed over the dielectric layer and over the first conductive feature; and a second conductive feature disposed on the first conductive feature, wherein the second conductive feature includes a first portion having a first bottom surface contacting a top surface of the first conductive feature and a second portion having a second bottom surface contacting a top surface of the dielectric layer.Type: ApplicationFiled: August 10, 2023Publication date: December 21, 2023Inventors: Hsiu-Wen Hsueh, Cai-Ling Wu, Ya-Ching Tseng, Chii-Ping Chen, Neng-Jye Yang
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Publication number: 20230411296Abstract: A semiconductor structure includes a semiconductor substrate, a dielectric layer, a tungsten plug, a conductive plug, and a contact barrier. The dielectric layer is over a semiconductor substrate. The tungsten plug is in the dielectric layer. The conductive plug is on the tungsten plug. The contact barrier includes a sidewall barrier on a sidewall of the conductive plug and a bottom barrier between the conductive plug and the tungsten plug. A thickness of the sidewall barrier is greater than a thickness of the bottom barrier.Type: ApplicationFiled: June 17, 2022Publication date: December 21, 2023Inventors: MENG-HSIEN LI, YING-HSIN HUNG, YU-SHAN YEH, LI-MIN CHEN, NENG-JYE YANG, KUO-BIN HUANG
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Patent number: 11830770Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises an interlayer dielectric (ILD) layer disposed over a substrate; a first conductive feature at least partially embedded in the ILD layer; a dielectric layer disposed over and aligned with the ILD layer, wherein a top surface of the dielectric layer is above a top surface of the first conductive feature; an etch stop layer (ESL) disposed over the dielectric layer and over the first conductive feature; and a second conductive feature disposed on the first conductive feature, wherein the second conductive feature includes a first portion having a first bottom surface contacting a top surface of the first conductive feature and a second portion having a second bottom surface contacting a top surface of the dielectric layer.Type: GrantFiled: May 20, 2022Date of Patent: November 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Hsiu-Wen Hsueh, Cai-Ling Wu, Ya-Ching Tseng, Chii-Ping Chen, Neng-Jye Yang
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Publication number: 20230349574Abstract: The present disclosure is at least directed to utilizing air curtain devices to form air curtains to separate and isolate areas in which respective workpieces are stored from a transfer compartment within a workpiece processing apparatus. The transfer compartment of the workpiece processing apparatus includes a robot configured to transfer or transport ones of the workpieces to and from these respective storage areas through the transfer compartment and to and from a tool compartment. A tool is present in the tool compartment for processing and refining the respective workpieces. Clean dry air (CDA) may be circulated through the respective storage areas. The air curtains formed by the air curtain devices and the circulation of CDA through the respective storage areas reduces the likelihood of the generation of defects, damages, and degradation of the workpieces when present within the workpiece processing apparatus.Type: ApplicationFiled: April 29, 2022Publication date: November 2, 2023Inventors: Chia-Wei WU, Hao YANG, Hsiao-Chieh CHOU, Chun-Hung CHAO, Jao Sheng HUANG, Neng-Jye YANG, Kuo-Bin HUANG
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Publication number: 20230335499Abstract: Some embodiments relate to a semiconductor structure including a dielectric layer over a substrate. A conductive body is disposed within the dielectric layer. The conductive body has a bottom surface continuously extending between opposing sidewalls. A first liner layer is disposed between the conductive body and the dielectric layer. The first liner layer extends along the opposing sidewalls of the conductive body. The first liner layer is laterally offset from a central region of the bottom surface of the conductive body by a non-zero distance.Type: ApplicationFiled: June 28, 2023Publication date: October 19, 2023Inventors: Hsiu-Wen Hsueh, Chii-Ping Chen, Neng-Jye Yang, Ya-Lien Lee, An-Jiao Fu, Ya-Ching Tseng
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Patent number: 11776818Abstract: An apparatus, semiconductor device and method of manufacture are presented, wherein a hard mask layer and one or more etch stop layers are etched in an etching chamber. In an embodiment the semiconductor device is placed on a mounting platform at a first height and an etch process is performed, then the semiconductor device is moved to a second height within the chamber and a second etch process is performed, with the rotational speed of the semiconductor device reduced during movements in order to reduce the chance of cross contamination.Type: GrantFiled: April 19, 2021Date of Patent: October 3, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wan Hsuan Hsu, Jao Sheng Huang, Yen-Chiu Kuo, Yu-Li Cheng, Ya Tzu Chen, Neng-Jye Yang, Chun-Li Chou
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Patent number: 11742291Abstract: Some embodiments relate to a semiconductor structure including a method for forming a semiconductor structure. The method includes forming a lower conductive structure within a first dielectric layer over a substrate. An upper dielectric structure is formed over the lower conductive structure. The upper dielectric structure comprises sidewalls defining an opening over the lower conductive structure. A first liner layer is selectively deposited along the sidewalls of the upper dielectric structure. A conductive body is formed within the opening and over the lower conductive structure. The conductive body has a bottom surface directly overlying a middle region of the lower conductive structure. The first layer is laterally offset from the middle region of the lower conductive structure by a non-zero distance.Type: GrantFiled: June 7, 2022Date of Patent: August 29, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiu-Wen Hsueh, Chii-Ping Chen, Neng-Jye Yang, Ya-Lien Lee, An-Jiao Fu, Ya-Ching Tseng
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Patent number: 11735426Abstract: An etchant is utilized to remove a semiconductor material. In some embodiments an oxidizer is added to the etchant in order to react with surrounding semiconductor material and form a protective layer. The protective layer is utilized to help prevent damage that could occur from the other components within the etchant.Type: GrantFiled: August 13, 2021Date of Patent: August 22, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURINGInventors: Jian-Jou Lian, Li-Min Chen, Neng-Jye Yang, Ming-Hsi Yeh, Shun Wu Lin, Kuo-Bin Huang
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Publication number: 20230207384Abstract: Embodiments described herein relate generally to methods for forming a conductive feature in a dielectric layer in semiconductor processing and structures formed thereby. In some embodiments, a structure includes a dielectric layer over a substrate, a surface modification layer, and a conductive feature. The dielectric layer has a sidewall. The surface modification layer is along the sidewall, and the surface modification layer includes phosphorous and carbon. The conductive feature is along the surface modification layer.Type: ApplicationFiled: March 6, 2023Publication date: June 29, 2023Inventors: Jian-Jou Lian, Kuo-Bin Huang, Neng-Jye Yang, Li-Min Chen
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Patent number: 11600521Abstract: Embodiments described herein relate generally to methods for forming a conductive feature in a dielectric layer in semiconductor processing and structures formed thereby. In some embodiments, a structure includes a dielectric layer over a substrate, a surface modification layer, and a conductive feature. The dielectric layer has a sidewall. The surface modification layer is along the sidewall, and the surface modification layer includes phosphorous and carbon. The conductive feature is along the surface modification layer.Type: GrantFiled: June 29, 2020Date of Patent: March 7, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jian-Jou Lian, Kuo-Bin Huang, Neng-Jye Yang, Li-Min Chen
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Publication number: 20230011792Abstract: The present disclosure provides a method of forming an interconnect structure. The method includes forming a metal layer over a substrate, the metal layer including a first metal; forming a capping layer on the metal layer; patterning the capping layer and the metal layer, thereby forming trenches in the metal layer; depositing a first dielectric layer in the trenches; removing the capping layer, resulting in the first dielectric layer protruding from a top surface of the metal layer; depositing a second dielectric layer over the first dielectric layer and the metal layer; forming an opening in the second dielectric layer, thereby partially exposing the top surface of the metal layer; and forming a conductive feature in the opening and in electrical coupling with the metal layer, the conductive feature including a second metal.Type: ApplicationFiled: July 9, 2021Publication date: January 12, 2023Inventors: Cai-Ling Wu, Hsiu-Wen Hsueh, Chii-Ping Chen, Po-Hsiang Huang, Chi-Feng Lin, Neng-Jye Yang
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Publication number: 20220334473Abstract: A method includes forming a tri-layer. The tri-layer includes a bottom layer; a middle layer over the bottom layer; and a top layer over the middle layer. The top layer includes a photo resist. The method further includes removing the top layer; and removing the middle layer using a chemical solution. The chemical solution is free from potassium hydroxide (KOH), and includes at least one of a quaternary ammonium hydroxide and a quaternary ammonium fluoride.Type: ApplicationFiled: June 30, 2022Publication date: October 20, 2022Inventors: Li-Min Chen, Kuo Bin Huang, Neng-Jye Yang, Chia-Wei Wu, Jian-Jou Lian
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Publication number: 20220319850Abstract: Aspects of the disclosure provide a method. The method includes forming a structure over a substrate, and forming a spacer layer on the structure, wherein the spacer layer has a recess. The method includes forming a mask layer over the spacer layer and in the recess, the mask layer including a first layer, a second layer and a third layer. The method includes patterning the third layer of the mask layer, and etching the first layer and the second layer of the mask layer to form an opening to expose the recess of the spacer layer, wherein the opening in the second layer has a first width; and. The method includes removing the second layer using a wet etchant, wherein the opening in the third layer has a second width, and the second with is greater than the first width.Type: ApplicationFiled: June 21, 2022Publication date: October 6, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Nai-Chia CHEN, Wan Hsuan HSU, Chia-Wei WU, Neng-Jye YANG, Chun-Li CHOU
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Publication number: 20220310526Abstract: Some embodiments relate to a semiconductor structure including a method for forming a semiconductor structure. The method includes forming a lower conductive structure within a first dielectric layer over a substrate. An upper dielectric structure is formed over the lower conductive structure. The upper dielectric structure comprises sidewalls defining an opening over the lower conductive structure. A first liner layer is selectively deposited along the sidewalls of the upper dielectric structure. A conductive body is formed within the opening and over the lower conductive structure. The conductive body has a bottom surface directly overlying a middle region of the lower conductive structure. The first layer is laterally offset from the middle region of the lower conductive structure by a non-zero distance.Type: ApplicationFiled: June 7, 2022Publication date: September 29, 2022Inventors: Hsiu-Wen Hsueh, Chii-Ping Chen, Neng-Jye Yang, Ya-Lien Lee, An-Jiao Fu, Ya-Ching Tseng
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Publication number: 20220277989Abstract: An opening is formed within a dielectric material overlying a semiconductor substrate. The opening may comprise a via portion and a trench portion. During the manufacturing process a treatment chemical is placed into contact with the exposed surfaces in order to release charges that have built up on the surfaces. By releasing the charges, a surface change potential difference is reduced, helping to prevent galvanic corrosion from occurring during further manufacturing.Type: ApplicationFiled: May 16, 2022Publication date: September 1, 2022Inventors: Yao-Wen Hsu, Ming-Che Ku, Neng-Jye Yang, Yu-Wen Wang
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Publication number: 20220277991Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises an interlayer dielectric (ILD) layer disposed over a substrate; a first conductive feature at least partially embedded in the ILD layer; a dielectric layer disposed over and aligned with the ILD layer, wherein a top surface of the dielectric layer is above a top surface of the first conductive feature; an etch stop layer (ESL) disposed over the dielectric layer and over the first conductive feature; and a second conductive feature disposed on the first conductive feature, wherein the second conductive feature includes a first portion having a first bottom surface contacting a top surface of the first conductive feature and a second portion having a second bottom surface contacting a top surface of the dielectric layer.Type: ApplicationFiled: May 20, 2022Publication date: September 1, 2022Inventors: Hsiu-Wen Hsueh, Cai-Ling Wu, Ya-Ching Tseng, Chii-Ping Chen, Neng-Jye Yang