Patents by Inventor Neng-Jye Yang

Neng-Jye Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200266065
    Abstract: A middle layer removal method is provided. The method includes providing a substrate having a structure formed on the substrate, and forming a spacer layer on the structure. The method includes forming a mask layer over the spacer layer, the mask layer including a first layer, a second layer over the first layer, and a third layer over the second layer. The method also includes patterning the third layer of the mask layer, and etching the first layer and the second layer of the mask layer to form an opening to expose a bottom surface of the second layer. The method further includes removing the second layer using a wet etchant.
    Type: Application
    Filed: May 8, 2020
    Publication date: August 20, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Nai-Chia CHEN, Wan Hsuan HSU, Chia-Wei WU, Neng-Jye YANG, Chun-Li CHOU
  • Patent number: 10699944
    Abstract: Embodiments described herein relate generally to methods for forming a conductive feature in a dielectric layer in semiconductor processing and structures formed thereby. In some embodiments, a structure includes a dielectric layer over a substrate, a surface modification layer, and a conductive feature. The dielectric layer has a sidewall. The surface modification layer is along the sidewall, and the surface modification layer includes phosphorous and carbon. The conductive feature is along the surface modification layer.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: June 30, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jian-Jou Lian, Kuo-Bin Huang, Neng-Jye Yang, Li-Min Chen
  • Patent number: 10685870
    Abstract: An opening is formed within a dielectric material overlying a semiconductor substrate. The opening may comprise a via portion and a trench portion. During the manufacturing process a treatment chemical is placed into contact with the exposed surfaces in order to release charges that have built up on the surfaces. By releasing the charges, a surface change potential difference is reduced, helping to prevent galvanic corrosion from occurring during further manufacturing.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: June 16, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yao-Wen Hsu, Ming-Che Ku, Neng-Jye Yang, Yu-Wen Wang
  • Patent number: 10676668
    Abstract: For a metal gate replacement integration scheme, the present disclosure describes removing a polysilicon gate electrode with a highly selective wet etch chemistry without damaging surrounding layers. For example, the wet etch chemistry can include one or more alkaline solvents with a steric hindrance amine structure, a buffer system that includes tetramethylammonium hydroxide (TMAH) and monoethanolamine (MEA), one or more polar solvents, and water.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: June 9, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Neng-Jye Yang, Kuo Bin Huang, Ming-Hsi Yeh, Shun Wu Lin, Yu-Wen Wang, Jian-Jou Lian, Shih Min Chang
  • Publication number: 20200161137
    Abstract: An etchant is utilized to remove a semiconductor material. In some embodiments an oxidizer is added to the etchant in order to react with surrounding semiconductor material and form a protective layer. The protective layer is utilized to help prevent damage that could occur from the other components within the etchant.
    Type: Application
    Filed: December 12, 2019
    Publication date: May 21, 2020
    Inventors: Jian-Jou Lian, Li-Min Chen, Neng-Jye Yang, Ming-Hsi Yeh, Shun Wu Lin, Kuo-Bin Huang
  • Patent number: 10658179
    Abstract: Aspects of the disclosure provide a method. The method includes providing a substrate having a structure formed on the substrate, and forming a spacer layer on the structure. Then, the method includes forming a mask layer over the spacer layer. The mask layer includes a first layer, a second layer over the first layer, and a third layer over the second layer. Further, the method includes patterning the third layer of the mask layer, and etching the first layer and the second layer of the mask layer with a dry etching process using the third layer as an etch mask to form an opening that exposes a portion of the spacer layer. Then, the method includes removing the second layer using a wet etchant before a formation of a backfill material layer in the opening and over the first layer.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: May 19, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Nai-Chia Chen, Wan Hsuan Hsu, Chia-Wei Wu, Neng-Jye Yang, Chun-Li Chou
  • Publication number: 20200105587
    Abstract: Embodiments described herein relate generally to methods for forming a conductive feature in a dielectric layer in semiconductor processing and structures formed thereby. In some embodiments, a structure includes a dielectric layer over a substrate, a surface modification layer, and a conductive feature. The dielectric layer has a sidewall. The surface modification layer is along the sidewall, and the surface modification layer includes phosphorous and carbon. The conductive feature is along the surface modification layer.
    Type: Application
    Filed: September 28, 2018
    Publication date: April 2, 2020
    Inventors: Jian-Jou Lian, Kuo-Bin Huang, Neng-Jye Yang, Li-Min Chen
  • Publication number: 20200083038
    Abstract: A semiconductor device and method of manufacture are provided. After a patterning of a middle layer, the middle layer is removed. In order to reduce or prevent damage to other underlying layers exposed by the patterning of the middle layer and intervening layers, an inhibitor is included within an etching process in order to inhibit the amount of material removed from the underlying layers.
    Type: Application
    Filed: November 18, 2019
    Publication date: March 12, 2020
    Inventors: Jian-Jou Lian, Yao-Wen Hsu, Neng-Jye Yang, Li-Min Chen, Chia-Wei Wu, Kuan-Lin Chen, Kuo Bin Huang
  • Publication number: 20200058502
    Abstract: Aspects of the disclosure provide a method. The method includes providing a substrate having a structure formed on the substrate, and forming a spacer layer on the structure. Then, the method includes forming a mask layer over the spacer layer. The mask layer includes a first layer, a second layer over the first layer, and a third layer over the second layer. Further, the method includes patterning the third layer of the mask layer, and etching the first layer and the second layer of the mask layer with a dry etching process using the third layer as an etch mask to form an opening that exposes a portion of the spacer layer. Then, the method includes removing the second layer using a wet etchant before a formation of a backfill material layer in the opening and over the first layer.
    Type: Application
    Filed: August 17, 2018
    Publication date: February 20, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Nai-Chia Chen, Wan Hsuan Hsu, Chia-Wei Wu, Neng-Jye Yang, Chun-Li Chou
  • Patent number: 10529572
    Abstract: An etchant is utilized to remove a semiconductor material. In some embodiments an oxidizer is added to the etchant in order to react with surrounding semiconductor material and form a protective layer. The protective layer is utilized to help prevent damage that could occur from the other components within the etchant.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: January 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jian-Jou Lian, Li-Min Chen, Neng-Jye Yang, Ming-Hsi Yeh, Shun Wu Lin, Kuo-Bin Huang
  • Patent number: 10483108
    Abstract: A semiconductor device and method of manufacture are provided. After a patterning of a middle layer, the middle layer is removed. In order to reduce or prevent damage to other underlying layers exposed by the patterning of the middle layer and intervening layers, an inhibitor is included within an etching process in order to inhibit the amount of material removed from the underlying layers.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: November 19, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jian-Jou Lian, Yao-Wen Hsu, Neng-Jye Yang, Li-Min Chen, Chia-Wei Wu, Kuan-Lin Chen, Kuo Bin Huang
  • Publication number: 20190333770
    Abstract: An etchant is utilized to remove a semiconductor material. In some embodiments an oxidizer is added to the etchant in order to react with surrounding semiconductor material and form a protective layer. The protective layer is utilized to help prevent damage that could occur from the other components within the etchant.
    Type: Application
    Filed: April 30, 2018
    Publication date: October 31, 2019
    Inventors: Jian-Jou Lian, Li-Min Chen, Neng-Jye Yang, Ming-Hsi Yeh, Shun Wu Lin, Kuo-Bin Huang
  • Publication number: 20190279876
    Abstract: A method of manufacturing a semiconductor device includes exposing a material to a semi-aqueous etching solution. The semi-aqueous etching solution comprises a solvent which chelates with the material and acts as a catalyst between the etching driving force and the material. As such, the etching driving force may be used to remove the material.
    Type: Application
    Filed: May 30, 2019
    Publication date: September 12, 2019
    Inventors: Yao-Wen Hsu, Jian-Jou Lian, Neng-Jye Yang, Chia-Wei Wu, Kuan-Lin Chen, Kuo Bin Huang, Li-Min Chen
  • Patent number: 10312073
    Abstract: A semi-aqueous wet clean system and method for removing carbon-containing silicon material (e.g., plasma residue) or nitrogen-containing silicon material (e.g., plasma residue) includes a hydroxyl-terminated organic compound, a diol, and a fluoride ion donor material. The system is configured to protect silicon oxide and amorphous silicon during a post-dry-etch wet clean. The wet clean system is configured to selectively remove carbon-containing or nitrogen-containing plasma residue. pH of the wet clean system can be modified to tune selectivity for removal of carbon-containing or nitrogen-containing plasma residues. As a result, positive TEOS recession of less than about 3 nanometers may be achieved. Additionally, the wet clean system can be adapted for reclamation and subsequent reuse.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: June 4, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yao-Wen Hsu, Jian-Jou Lian, Neng-Jye Yang, Kuan-Lin Chen
  • Patent number: 10312106
    Abstract: A method of manufacturing a semiconductor device includes exposing a material to a semi-aqueous etching solution. The semi-aqueous etching solution comprises a solvent which chelates with the material and acts as a catalyst between the etching driving force and the material. As such, the etching driving force may be used to remove the material.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: June 4, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yao-Wen Hsu, Jian-Jou Lian, Neng-Jye Yang, Chia-Wei Wu, Kuan-Lin Chen, Kuo Bin Huang, Li-Min Chen
  • Publication number: 20190119570
    Abstract: For a metal gate replacement integration scheme, the present disclosure describes removing a polysilicon gate electrode with a highly selective wet etch chemistry without damaging surrounding layers. For example, the wet etch chemistry can include one or more alkaline solvents with a steric hindrance amine structure, a buffer system that includes tetramethylammonium hydroxide (TMAH) and monoethanolamine (MEA), one or more polar solvents, and water.
    Type: Application
    Filed: December 14, 2018
    Publication date: April 25, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Neng-Jye YANG, Kuo Bin HUANG, Ming-Hsi YEH, Shun Wu LIN, Yu-Wen WANG, Jian-Jou LIAN, Shih Min CHANG
  • Publication number: 20190064658
    Abstract: A method includes forming a tri-layer. The tri-layer includes a bottom layer; a middle layer over the bottom layer; and a top layer over the middle layer. The top layer includes a photo resist. The method further includes removing the top layer; and removing the middle layer using a chemical solution. The chemical solution is free from potassium hydroxide (KOH), and includes at least one of a quaternary ammonium hydroxide and a quaternary ammonium fluoride.
    Type: Application
    Filed: October 3, 2017
    Publication date: February 28, 2019
    Inventors: Li-Min Chen, Kuo Bin Huang, Neng-Jye Yang, Chia-Wei Wu, Jian-Jou Lian
  • Publication number: 20190067088
    Abstract: An opening is formed within a dielectric material overlying a semiconductor substrate. The opening may comprise a via portion and a trench portion. During the manufacturing process a treatment chemical is placed into contact with the exposed surfaces in order to release charges that have built up on the surfaces. By releasing the charges, a surface change potential difference is reduced, helping to prevent galvanic corrosion from occurring during further manufacturing.
    Type: Application
    Filed: February 15, 2018
    Publication date: February 28, 2019
    Inventors: Yao-Wen Hsu, Ming-Che Ku, Neng-Jye Yang, Yu-Wen Wang
  • Publication number: 20190035637
    Abstract: A method of manufacturing a semiconductor device includes exposing a material to a semi-aqueous etching solution. The semi-aqueous etching solution comprises a solvent which chelates with the material and acts as a catalyst between the etching driving force and the material. As such, the etching driving force may be used to remove the material.
    Type: Application
    Filed: November 1, 2017
    Publication date: January 31, 2019
    Inventors: Yao-Wen Hsu, Jian-Jou Lian, Neng-Jye Yang, Chia-Wei Wu, Kuan-Lin Chen, Kuo Bin Huang, Li-Min Chen
  • Patent number: 10179878
    Abstract: For a metal gate replacement integration scheme, the present disclosure describes removing a polysilicon gate electrode with a highly selective wet etch chemistry without damaging surrounding layers. For example, the wet etch chemistry can include one or more alkaline solvents with a steric hindrance amine structure, a buffer system that includes tetramethylammonium hydroxide (TMAH) and monoethanolamine (MEA), one or more polar solvents, and water.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: January 15, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Neng-Jye Yang, Kuo Bin Huang, Ming-Hsi Yeh, Shun Wu Lin, Yu-Wen Wang, Jian-Jou Lian, Shih Min Chang