Abstract: The present disclosure generally relates to efficient block usage after ungraceful shutdown (UGSD) events. After a UGSD event, a host device is alerted by the data storage device that a QLC block that was being used prior to the UGSD event is experiencing an ongoing block recovery and that the block is not yet available to accept new data. The block is then checked to determine whether the block can continue to be used for the programming that was occurring at the time of the UGSD event. Once a determination is made, the data storage device notifies the host device so that normal operations may continue. Additionally, the amount of free blocks available for programming is monitored during UGSD events so that the host device can be warned if a power loss halt is triggered.

Abstract: For solid state drive (SSD) or other memory system formed of multiple memory dies, techniques are presented for operation in a standby mode with increased power savings. The memory dies are operable in a regular standby mode and in a low power standby mode. Based upon the amount of current each of the memory dies in the regular standby mode, when the device goes into standby the memory dies that draw higher amounts of current when in the regular standby mode are instead placed into the low power standby mode. The amount of current drawn by each of the memory die in the regular standby mode can be determined for each of the memory dies at die sort or as part of the memory test process, or can be determine by an assembled SSD itself.

Abstract: A data storage device is configured to mark data for refresh in response to determining that a first measured temperature associated with writing the data to the memory exceeds a first threshold. The data storage device is further configured to refresh the marked data in response to determining that a second measured temperature associated with the memory is below a second threshold.

Abstract: Methods and apparatus for storing parity bits in an available over provisioning (OP) space to recover data lost from an entire memory block. For example, a data storage device may receive data from a host device, write the data to a block, and generate a corresponding block parity. The device may then determine a bit error rate (BER) of the block and an average programming duration to write the data written to the block, calculate a probability of the block becoming defective based on the BER and the average programming duration, and comparing the probability of the block to a set of probabilities respectively corresponding to a set of worst-performing blocks in a NVM. Thereafter, the device may write the block parity to an available over provisioning (OP) space in the NVM responsive to the probability of the block being greater than any probability in the set of probabilities.

Abstract: A storage system and method for boundary wordline data retention handling are provided. In one embodiment, the storage system includes a memory having a single-level cell (SLC) block and a multi-level cell (MLC) block. The system determines if the boundary wordline in the MLC block has a data retention problem (e.g., by determining how long it has been since the boundary wordline was programmed). To address the data retention problem, the storage system can copy data from a wordline in the SLC block that corresponds to the boundary wordline in the MLC block to a wordline in another SLC block prior to de-committing the data in the SLC block. Alternatively, the storage system can reprogram the data in the boundary wordline using a double fine programing technique.

Abstract: The present disclosure generally relates to efficient block usage after ungraceful shutdown (UGSD) events. After a UGSD event, a host device is alerted by the data storage device that a QLC block that was being used prior to the UGSD event is experiencing an ongoing block recovery and that the block is not yet available to accept new data. The block is then checked to determine whether the block can continue to be used for the programming that was occurring at the time of the UGSD event. Once a determination is made, the data storage device notifies the host device so that normal operations may continue. Additionally, the amount of free blocks available for programming is monitored during UGSD events so that the host device can be warned if a power loss halt is triggered.

Abstract: Methods and apparatus for storing parity bits in an available over provisioning (OP) space to recover data lost from an entire memory block. For example, a data storage device may receive data from a host device, write the data to a block, and generate a corresponding block parity. The device may then determine a bit error rate (BER) of the block and an average programming duration to write the data written to the block, calculate a probability of the block becoming defective based on the BER and the average programming duration, and comparing the probability of the block to a set of probabilities respectively corresponding to a set of worst-performing blocks in a NVM. Thereafter, the device may write the block parity to an available over provisioning (OP) space in the NVM responsive to the probability of the block being greater than any probability in the set of probabilities.

Abstract: A storage system and method for boundary wordline data retention handling are provided. In one embodiment, the storage system includes a memory having a single-level cell (SLC) block and a multi-level cell (MLC) block. The system determines if the boundary wordline in the MLC block has a data retention problem (e.g., by determining how long it has been since the boundary wordline was programmed). To address the data retention problem, the storage system can copy data from a wordline in the SLC block that corresponds to the boundary wordline in the MLC block to a wordline in another SLC block prior to de-committing the data in the SLC block. Alternatively, the storage system can reprogram the data in the boundary wordline using a double fine programing technique.

Abstract: The present disclosure discloses a memory device including a control system for thermal throttling. The control system acquires the temperature of a non-volatile memory element from a temperature detector at a first frequency. Upon determining that the temperature of the non-volatile memory element is above a pre-determined threshold, the control system acquires the temperature of the non-volatile memory element from the temperature detector at a second frequency that is higher than the first frequency and activates the thermal throttling for the non-volatile memory element.

Abstract: Techniques are described for performing a read scan process on a non-volatile memory system in order to determine memory blocks that may have a high bit error rate, where if such blocks are found they can be refreshed. Rather than work through the blocks of a memory system sequentially based on the physical block addresses, the memory system maintains a measure of data quality, such as an estimated or average bit error rate, for multi-block groups. For example, the groups can correspond to regions of memory die in the system. The groups are ranked by their data quality, with the groups being scanned in order of the data quality. The blocks within a group can also be ranked, based on factors such as the program/erase count.

Abstract: For solid state drive (SSD) or other memory system formed of multiple memory dies, techniques are presented for operation in a standby mode with increased power savings. The memory dies are operable in a regular standby mode and in a low power standby mode. Based upon the amount of current each of the memory dies in the regular standby mode, when the device goes into standby the memory dies that draw higher amounts of current when in the regular standby mode are instead placed into the low power standby mode. The amount of current drawn by each of the memory die in the regular standby mode can be determined for each of the memory dies at die sort or as part of the memory test process, or can be determine by an assembled SSD itself.

Abstract: Embodiments of the present disclosure relate to physical secure erase (PSE) of solid state drives (SSDs). One embodiment of a method of PSE of a SSD includes receiving a PSE command, erasing the memory cells of the blocks, programming the memory cells, and programming the select gates to a portion of the blocks. One embodiment of a SSD includes a controller and a plurality of blocks having a plurality of NAND strings. Each NAND string includes connected in series a select gate drain, memory cells, and a select gate source. The SSD includes a memory erasing instruction that cause the controller to erase the memory cells of the block, program the memory cells, and increase the threshold voltage to the select gate drain and/or the select gate source of some of the NAND strings from the blocks.

Abstract: An exemplary method to rank blocks of a non-volatile memory device includes: for each of a plurality of blocks of a memory device, determining a respective erase health metric (EHM) for each of the blocks by combining an erase difficulty metric and an age metric, including: calculating the erase difficulty metric for a respective block based on erase performance metrics obtained during erase phases of an erase operation performed on the respective block, and determining the age metric for the respective block based on a total number of erase operations performed on the respective block during its lifespan. After determining the respective EHM for each of the blocks, the method includes ranking blocks in accordance with the determined respective EHMs, and selecting a block of the plurality of blocks in accordance with the rankings, and writing data to the selected block.

Abstract: A data storage device is configured to mark data for refresh in response to determining that a first measured temperature associated with writing the data to the memory exceeds a first threshold. The data storage device is further configured to refresh the marked data in response to determining that a second measured temperature associated with the memory is below a second threshold.

Abstract: A storage system and method for performing high-speed read and write operations are disclosed. In general, these embodiments discuss ways for performing a fast read in response to determining that the fast read will probably not have a negative impact on performance due to error correction and performing a fast write in response to determining that a storage system criterion is satisfied.

Abstract: Techniques are described for performing a read scan process on a non-volatile memory system in order to determine memory blocks that may have a high bit error rate, where if such blocks are found they can be refreshed. Rather than work through the blocks of a memory system sequentially based on the physical block addresses, the memory system maintains a measure of data quality, such as an estimated or average bit error rate, for multi-block groups. For example, the groups can correspond to regions of memory die in the system. The groups are ranked by their data quality, with the groups being scanned in order of the data quality. The blocks within a group can also be ranked, based on factors such as the program/erase count.

Abstract: A data storage device is configured to mark data for refresh in response to determining that a first measured temperature associated with writing the data to the memory exceeds a first threshold. The data storage device is further configured to refresh the marked data in response to determining that a second measured temperature associated with the memory is below a second threshold.

Abstract: Over a period of operation, non-volatile memory can develop a residual resistance that is impractical to remove. For example, in a NAND string of memory cells, trapped charge may build up in a region between the bit lines and drain side select gates, so that even when all the devices of a NAND string are in an “on” state, the NAND string will not conduct. This effect will skew both hard bit data determinations, indicating the data state of a selected memory cell, and soft bit data determinations which may correlate to the reliability of the hard bit data. Techniques are described to factor in such excessive residual resistance when determining the soft bit data.

Abstract: A storage device with a memory may include improved endurance and programming speed by modifying the programming states of the memory blocks. For example, the blocks may be three bit memory blocks, but a dynamic reassignment of verify levels and read margins can result in the block acting like a two bit memory block. Memory blocks may be designed for a certain number of bits per cell (i.e. number of states) and the programming is based on that number. However, single level cell (SLC) programming is still possible in addition to programming according to the number of bits per cell that the memory is designed for. Multiple SLC programming steps can be used to modify the number of states for certain memory cells by the memory controller.

Abstract: On a non-volatile memory circuit, peripheral circuitry generates programming voltages based on parameter values. If parameter values are incorrectly translated into programming voltages, data may be over-programmed, resulting in high bit error rates (BERs). The memory system can monitor the error rates using memory cell voltage distributions for different portions of the memory and look for signatures of such incorrect implementation. For example, by monitoring the BER along word lines that are most prone to error due to incorrectly implemented programming parameters, the memory system can determine if the programming parameters for the corresponding portion of a memory device indicate such anomalous behavior. If such a signature is found, the memory system checks to see whether the programming parameters should be adjusted, such as by comparing the programming parameters used on one die to programming parameters used on another die of the memory system, and adjust the programming parameters accordingly.