Patents by Inventor Nian Niles Yang
Nian Niles Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170371755Abstract: A non-volatile memory system includes a plurality of non-volatile data memory cells arranged into groups of data memory cells, a plurality of select devices connected to the groups of data memory cells, a selection line connected to the select devices, a plurality of data word lines connected to the data memory cells, and one or more control circuits connected to the selection line and the data word lines. The one or more control circuits are configured to determine whether the select devices are corrupted. If the select devices are corrupted, then the one or more control circuits repurpose one of the word lines (e.g., the first data word line closet to the select devices) to be another selection line, thus operating the memory cells connected to the repurposed word line as select devices.Type: ApplicationFiled: June 23, 2016Publication date: December 28, 2017Applicant: SANDISK TECHNOLOGIES LLCInventors: Nian Niles Yang, Jiahui Yuan, Grishma Shah, Xinde Hu, Lanlan Gu, Bin Wu
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Patent number: 9846554Abstract: A storage system and method for generating block allocation groups based on deterministic data patterns are provided. A storage system is provided comprising a memory comprising a plurality of blocks and a controller. The controller is configured to infer characteristics of the memory from data patterns of data stored in the plurality of blocks; and group the plurality of blocks based on the inferred characteristics of the memory.Type: GrantFiled: August 4, 2016Date of Patent: December 19, 2017Assignee: SanDisk Technologies LLCInventors: Joanna Lai, Nian Niles Yang
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Patent number: 9837146Abstract: Systems, methods and/or devices are used to adjust a read property for a memory portion of non-volatile memory. In one aspect, in response to receiving a program request, the device: detects a first temperature of the memory portion; and stores first temperature data corresponding to the detected first temperature. In response to receiving a read request, the device performs an adjustment determination, including: detecting a second temperature of the memory portion of the non-volatile memory, retrieving the stored first temperature data, and determining, in accordance with the detected second temperature and the retrieved first temperature data, whether to perform the read using an adjusted read property. In accordance with a determination to perform the read using the adjusted read property, the device performs a read on the memory portion using the adjusted read property.Type: GrantFiled: June 28, 2016Date of Patent: December 5, 2017Assignee: SanDisk Technologies LLCInventors: Nian Niles Yang, Chris Nga Yee Yip
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Patent number: 9811267Abstract: A non-volatile storage apparatus comprises a controller, one or more memory packages, a system temperature sensor, and one or more memory temperature sensors. The system temperature sensor is located at or on the controller. Each of the one or more memory temperature sensors are positioned at one of the one or more memory packages. The controller monitors system temperature using the system temperature sensor. If the system temperature is above a first threshold, then temperature is sensed at the memory packages using the one or more memory temperature sensors. Individual memory packages have their performance throttled if their temperature exceeds a second threshold.Type: GrantFiled: October 14, 2016Date of Patent: November 7, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Nian Niles Yang, Grishma Shah, Phil Reusswig, Dmitry Vaysman
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Publication number: 20170309340Abstract: Read operations are performed in a multi-plane memory device. A state machine interfaces an external controller to each plane of memory cells to allow reading from selected word lines in the planes. In one approach, different types of read operations are performed in different planes, such as a multi-level cell read, e.g., a lower, middle or upper page read and a single-level cell (SLC) read. When the read operation in one plane uses fewer read voltages than another plane, the read data can be output early from the one plane while read operations continue on the other plane. The external controller can also command a cache release for one plane after outputting data from the caches of another plane. Read voltages can be set for each plane in a respective set of registers.Type: ApplicationFiled: June 20, 2017Publication date: October 26, 2017Applicant: SanDisk Technologies LLCInventors: Grishma Shah, Yan Li, Jian Chen, Kenneth Louie, Nian Niles Yang
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Publication number: 20170309338Abstract: Read operations are performed in a multi-plane memory device. A state machine interfaces an external controller to each plane of memory cells to allow reading from selected word lines in the planes. In one approach, different types of read operations are performed in different planes, such as a multi-level cell read, e.g., a lower, middle or upper page read and a single-level cell (SLC) read. When the read operation in one plane uses fewer read voltages than another plane, the read data can be output early from the one plane while read operations continue on the other plane. The external controller can also command a cache release for one plane after outputting data from the caches of another plane. Read voltages can be set for each plane in a respective set of registers.Type: ApplicationFiled: April 26, 2016Publication date: October 26, 2017Applicant: SanDisk Technologies Inc.Inventors: Grishma Shah, Yan Li, Jian Chen, Kenneth Louie, Nian Niles Yang
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Patent number: 9792995Abstract: Read operations are performed in a multi-plane memory device. A state machine interfaces an external controller to each plane of memory cells to allow reading from selected word lines in the planes. In one approach, different types of read operations are performed in different planes, such as a multi-level cell read, e.g., a lower, middle or upper page read and a single-level cell (SLC) read. When the read operation in one plane uses fewer read voltages than another plane, the read data can be output early from the one plane while read operations continue on the other plane. The external controller can also command a cache release for one plane after outputting data from the caches of another plane. Read voltages can be set for each plane in a respective set of registers.Type: GrantFiled: April 26, 2016Date of Patent: October 17, 2017Assignee: SanDisk Technologies LLCInventors: Grishma Shah, Yan Li, Jian Chen, Kenneth Louie, Nian Niles Yang
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Patent number: 9792998Abstract: Systems and methods for detecting program disturb and for programming/reading based on the detected program disturb are disclosed. Program disturb comprises unintentionally programming an unselected section of memory during the program operation of the selected section of memory. To reduce the effect of program disturb, the section of memory is analyzed in a predetermined state (such as the erase state) for program disturb. In response to identifying signs of program disturb, the voltages used to program the section of memory (such as the program verify levels for programming data into the cells of the section of memory) may be adjusted. Likewise, when reading data from the section of memory, the read voltages may be adjusted based on the adjusted voltages used for programming. In this way, using the adjusted programming and reading voltages, the effect of program disturb may be reduced.Type: GrantFiled: March 29, 2016Date of Patent: October 17, 2017Assignee: SanDisk Technologies LLCInventors: Nian Niles Yang, Chris Yip, Grishma Shah
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Publication number: 20170287568Abstract: Systems and methods for detecting program disturb and for programming/reading based on the detected program disturb are disclosed. Program disturb comprises unintentionally programming an unselected section of memory during the program operation of the selected section of memory. To reduce the effect of program disturb, the section of memory is analyzed in a predetermined state (such as the erase state) for program disturb. In response to identifying signs of program disturb, the voltages used to program the section of memory (such as the program verify levels for programming data into the cells of the section of memory) may be adjusted. Likewise, when reading data from the section of memory, the read voltages may be adjusted based on the adjusted voltages used for programming. In this way, using the adjusted programming and reading voltages, the effect of program disturb may be reduced.Type: ApplicationFiled: March 29, 2016Publication date: October 5, 2017Applicant: SanDisk Technologies, Inc.Inventors: Nian Niles Yang, Chris Yip, Grishma Shah
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Publication number: 20170255399Abstract: An exemplary method to rank blocks of a non-volatile memory device includes: for each of a plurality of blocks of a memory device, determining a respective erase health metric (EHM) for each of the blocks by combining an erase difficulty metric and an age metric, including: calculating the erase difficulty metric for a respective block based on erase performance metrics obtained during erase phases of an erase operation performed on the respective block, and determining the age metric for the respective block based on a total number of erase operations performed on the respective block during its lifespan. After determining the respective EHM for each of the blocks, the method includes ranking blocks in accordance with the determined respective EHMs, and selecting a block of the plurality of blocks in accordance with the rankings, and writing data to the selected block.Type: ApplicationFiled: October 4, 2016Publication date: September 7, 2017Inventors: Nian Niles Yang, Alexandra Bauche
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Publication number: 20170255403Abstract: A data storage device is configured to mark data for refresh in response to determining that a first measured temperature associated with writing the data to the memory exceeds a first threshold. The data storage device is further configured to refresh the marked data in response to determining that a second measured temperature associated with the memory is below a second threshold.Type: ApplicationFiled: May 27, 2016Publication date: September 7, 2017Inventors: ERAN SHARON, NIAN NILES YANG, IDAN ALROD, EVGENY MEKHANIK, MARK SHLICK, JOANNA LAI
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Patent number: 9753657Abstract: A storage device with a charge trapping (CT) based memory may include improved data retention (DR) performance. The CT memory may be 3D memory that uses a charge storage layer for storing charge may have unique data retention behavior. Memory blocks using a charge storage layer may be dynamically detected and reconditioned and re-programmed to improve memory characteristics, such as data retention. The reconditioning may include a dedicated erase cycle for a block that improves the data retention.Type: GrantFiled: September 18, 2015Date of Patent: September 5, 2017Assignee: SanDisk Technologies LLCInventors: Nian Niles Yang, James Fitzpatrick, Jiahui Yuan
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Patent number: 9740425Abstract: A data storage device includes a memory. A method includes de-allocating a first region of a group of regions of the memory during a wear leveling process based on a determination that the first region is associated with a first tag of a set of tags. Each region of the group of regions is assigned to a tag of the set of tags based on a health metric associated with the region. The health metric is based on a bit error rate (BER), a program/erase cycle (PEC) count, a PEC condition metric, or a combination thereof. In response to selecting the first region, information is copied from the first region to a second region of the memory during the wear leveling process.Type: GrantFiled: December 16, 2014Date of Patent: August 22, 2017Assignee: SanDisk Technologies LLCInventors: Swati Bakshi, Nian Niles Yang, Alexei Naberezhnov, Xinde Hu
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Patent number: 9721662Abstract: A non-volatile memory system includes a plurality of NAND strings (or other arrangements) that form a monolithic three dimensional memory structure, bit lines, word lines, and one or more control circuits. Multiple NAND strings of the plurality of NAND strings have different select gates connected to different select lines. The multiple NAND strings are connected to a common bit line. The multiple NAND strings are connected to a common word line via their respective different select gates. The one or more control circuits concurrently program multiple memory cells on the multiple NAND strings.Type: GrantFiled: January 13, 2016Date of Patent: August 1, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Nian Niles Yang, Chris Avila
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Patent number: 9715938Abstract: A non-volatile memory system includes a plurality of groups of connected non-volatile memory cells (e.g., charge trapping memory cells), a select line, and a plurality of select gates connected to the select line. Each select gate is connected at an end (e.g. source end or drain side) of one of the groups of memory cells. The system includes one or more control circuits that are configured to determine whether the select gates are abnormal. If a select gate is determined to be abnormal, then one of the memory cells connected to the select gate is converted to operate as a select gate. The system will then perform memory operations by operating the converted memory cell as a select gate.Type: GrantFiled: September 21, 2015Date of Patent: July 25, 2017Assignee: SanDisk Technologies LLCInventors: Nian Niles Yang, Jim Fitzpatrick, Yiwei Song
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Patent number: 9711231Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of a memory cell can shift depending on when the read operation occurs. In one aspect, read voltages are set and optimized based on a time period since a last sensing operation. A timing device such as an n-bit digital counter may be provided for each block of memory cells to track the time. The counter is set to all 1's when the device is powered on. When a sensing operation occurs, the counter is periodically incremented based on a clock. When a next read operation occurs, the value of the counter is cross-referenced to an optimal set of read voltage shifts. Each block of cells may have its own counter, where the counters are incremented using a local or global clock.Type: GrantFiled: June 24, 2016Date of Patent: July 18, 2017Assignee: SanDisk Technologies LLCInventors: Chris Yip, Philip Reusswig, Nian Niles Yang, Grishma Shah, Abuzer Azo Dogan, Biswajit Ray, Mohan Dunga, Joanna Lai, Changyuan Chen
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Publication number: 20170200501Abstract: A non-volatile memory system includes a plurality of NAND strings (or other arrangements) that form a monolithic three dimensional memory structure, bit lines, word lines, and one or more control circuits. Multiple NAND strings of the plurality of NAND strings have different select gates connected to different select lines. The multiple NAND strings are connected to a common bit line. The multiple NAND strings are connected to a common word line via their respective different select gates. The one or more control circuits concurrently program multiple memory cells on the multiple NAND strings.Type: ApplicationFiled: January 13, 2016Publication date: July 13, 2017Applicant: SANDISK TECHNOLOGIES INC.Inventors: Nian Niles Yang, Chris Avila
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Publication number: 20170200492Abstract: Systems, methods and/or devices are used to adjust a read property for a memory portion of non-volatile memory. In one aspect, in response to receiving a program request, the device: detects a first temperature of the memory portion; and stores first temperature data corresponding to the detected first temperature. In response to receiving a read request, the device performs an adjustment determination, including: detecting a second temperature of the memory portion of the non-volatile memory, retrieving the stored first temperature data, and determining, in accordance with the detected second temperature and the retrieved first temperature data, whether to perform the read using an adjusted read property. In accordance with a determination to perform the read using the adjusted read property, the device performs a read on the memory portion using the adjusted read property.Type: ApplicationFiled: June 28, 2016Publication date: July 13, 2017Inventors: Nian Niles Yang, Chris Nga Yee Yip
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Patent number: 9672940Abstract: In response to a request to read data, the non-volatile memory system identifies the physical block that is storing the requested data. Read parameters associated with the physical block are also identified. The read parameters include bit error rate information. The memory system chooses whether to use a read process with a faster sense time or a read process with a slower sense time based on the bit error rate information and temperature data. The requested data is read from the identified physical block using the chosen read process configured by at least a subset of the read parameters.Type: GrantFiled: August 18, 2016Date of Patent: June 6, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Phil Reusswig, Nian Niles Yang, Grishma Shah
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Publication number: 20170139761Abstract: Systems, methods and/or devices are used to adjust error metrics for a memory portion of non-volatile memory in a storage device. In one aspect, a first write and a first read are performed on the memory portion. In accordance with results of the first read, a first error metric value for the memory portion is determined. In accordance with a determination that the first error metric value exceeds a first threshold value, an entry for the memory portion is added to a table. After the first write, when a second write to the memory portion is performed, it is determined whether the entry for the memory portion is present in the table. In accordance with a determination that the entry for the memory portion is present in the table, the second write uses a first error adjustment characteristic that is determined in accordance with the first error metric value.Type: ApplicationFiled: June 28, 2016Publication date: May 18, 2017Inventors: Yiwei Song, Nian Niles Yang, James Fitzpatrick