Abstract: A non-volatile storage system identifies a word line with an open neighbor word line and determines whether data stored in non-volatile memory cells connected to the identified word line has an error condition. If the data does have an error condition, then an attempt is made to fix the data and the open neighbor word line is checked for errors. If the open neighbor word line has errors, then memory cells connected to the open neighbor word line are programmed with pseudo data.

Abstract: A device includes a memory including a first set of storage elements and a second set of storage elements. The device further includes circuitry coupled to the memory and configured to perform a data folding operation to fold second data from the second set of storage elements with respect to first data stored at the first set of storage elements. Each storage element of the first set of storage elements is designated to store at least three bits per storage element, and each storage element of the second set of storage elements is designated to store at least two bits per storage element.

Abstract: A storage system and method for using hybrid blocks with sub-block erase operations are provided. In one embodiment, a storage system is provided comprising a memory comprising a block, wherein the block comprises a first sub-block and a second sub-block; and a controller in communication with the memory. The controller is configured to erase the first sub-block, wherein the second sub-block is programmed; and program the first sub-block to fewer bits per cell than the second sub-block is programmed to. Other embodiments are provided.

Abstract: A device includes a memory device and a controller. The controller is coupled to the memory device. The controller is configured to, in response to receiving a request to perform a memory access at the memory device, determine that the memory device has a characteristic indicative of a temperature crossing. The controller is also configured to, in response to determining that the memory device has the characteristic indicative of the temperature crossing, determine that the memory device satisfies an availability criterion. The controller is further configured to, in response to determining that the memory device satisfies the availability criterion, increase a temperature of the memory device by performing memory operations on the memory device until detecting a condition related to the temperature.

Abstract: A non-volatile memory system includes a plurality of groups of connected non-volatile memory cells (e.g., charge trapping memory cells), a select line, and a plurality of select gates connected to the select line. Each select gate is connected at an end (e.g. source end or drain side) of one of the groups of memory cells. The system includes one or more control circuits that are configured to determine whether the select gates are abnormal. If a select gate is determined to be abnormal, then one of the memory cells connected to the select gate is converted to operate as a select gate. The system will then perform memory operations by operating the converted memory cell as a select gate.

Abstract: A storage device with a charge trapping (CT) based memory may include improved data retention (DR) performance. The CT memory may be 3D memory that uses a charge storage layer for storing charge may have unique data retention behavior. Memory blocks using a charge storage layer may be dynamically detected and reconditioned and re-programmed to improve memory characteristics, such as data retention. The reconditioning may include a dedicated erase cycle for a block that improves the data retention.

Abstract: The various implementations described herein include systems, methods and/or devices used to enable multi-phase erasure in a storage device. The method includes performing an erase operation on a portion of one or more non-volatile memory devices, by performing a sequence of erase phase operations until an erase operation stop condition is satisfied. Each erase phase operation includes: performing an erase phase on the portion of the non-volatile memory devices using an erase voltage, and determining an erase phase statistic for the erase phase. For each erase phase operation in the sequence of erase phase operations, other than a first erase phase operation, the erase voltage used when performing the erase phase operation is equal to the erase voltage used when performing a prior erase phase operation in the sequence of erase phase operations plus an erase voltage increment based on the erase phase statistic for the prior erase phase operation.

Abstract: A storage device with a memory may include improved endurance and programming speed by modifying the programming states of the memory blocks. For example, the blocks may be three bit memory blocks, but a dynamic reassignment of verify levels and read margins can result in the block acting like a two bit memory block. Memory blocks may be designed for a certain number of bits per cell (i.e. number of states) and the programming is based on that number. However, single level cell (SLC) programming is still possible in addition to programming according to the number of bits per cell that the memory is designed for. Multiple SLC programming steps can be used to modify the number of states for certain memory cells by the memory controller.

Abstract: A method may be performed in a data storage device that includes a memory and a controller, in response to a request to read data from the memory. The data is located within a first word line of the memory. The method includes accessing the data from the first word line and determining, based on a probability threshold, whether to perform a remedial action with respect to a second word line.

Abstract: A memory system or flash card may include memory maintenance scheduling that improves the endurance of memory. Certain parameters, such as temperature, are measured and used for scheduling maintenance. For example, memory maintenance may be performed or postponed depending on the ambient temperature of the card. The memory maintenance operations may be ranked or classified (e.g. in a memory maintenance queue based on priority) to correspond with threshold values of the parameters for a more efficient scheduling of memory maintenance. For example, at a low temperature threshold, only high priority maintenance operations are performed, while at a higher temperature threshold, any priority maintenance operation is performed.

Abstract: A data storage device may be configured to write first data to a first set of storage elements of a non-volatile memory and to write second data to a second set of storage elements of the non-volatile memory. The first data may be processed by a data shaping operation, and the second data may not be processed by the data shaping operation. The data storage device may be further configured to read a representation of the second data from the second set of storage cells and to determine a block health metric of a portion of the non-volatile memory based on the representation of the second data. The portion may include the first set of storage elements and the second set of storage elements. As an illustrative, non-limiting example, the first portion may be a first block of the non-volatile memory.

Abstract: A memory system or flash memory device may include identify a bit error rate (BER) mapping for the memory. The BER mapping may be used for identifying erroneous bits, managing them, and using them for the system maintenance and system recovery. A complete BER map may be stored in main memory while a cached version of the BER map may be stored in random access memory (RAM). The cached version may identify only the top and bottom bits rather than the complete map. The cached BER map may be updated based on future reads and future programming may rely on the cached BER map for selecting blocks to program.

Abstract: A memory system or flash card may monitor the health of memory and the user data stored by detecting and storing a number of bits in error for each block. This detection can be used to determine where user data should be programmed and which blocks should be cycled. The erratic bits are detected after a programming and the listing for each block is updated. When the erratic bits exceed a threshold for a particular block, that block may be cycled or retired.

Abstract: A data storage device includes a memory. A method includes de-allocating a first region of a group of regions of the memory during a wear leveling process based on a determination that the first region is associated with a first tag of a set of tags. Each region of the group of regions is assigned to a tag of the set of tags based on a health metric associated with the region. The health metric is based on a bit error rate (BER), a program/erase cycle (PEC) count, a PEC condition metric, or a combination thereof. In response to selecting the first region, information is copied from the first region to a second region of the memory during the wear leveling process.

Abstract: A memory system or flash card may monitor the health of memory and the user data stored by detecting and storing a number of bits in error for each block. This detection can be used to determine where user data should be programmed and which blocks should be cycled. The erratic bits are detected after a programming and the listing for each block is updated. When the erratic bits exceed a threshold for a particular block, that block may be cycled or retired.

Abstract: A data storage device that includes a controller and a non-volatile memory may perform a method that includes comparing, in the controller, first parameter values of a first group of parameter values to second parameter values of a second group of parameter values. The second parameter values of the second group of parameter values are associated with a scheduled non-volatile memory operation. The first parameter values correspond to parameter values that are in the non-volatile memory. The method includes sending, from the controller to the non-volatile memory, a parameter value of the second group in response to determining that the parameter value differs from a corresponding parameter value of the first group.

Abstract: Non-volatile memory and methods of reading non-volatile memory are provided for managing and reducing read related disturb. Techniques are introduced to reduce read disturb using state-dependent read pass voltages for particular word lines during a read operation. Because of their proximity to a selected word line, adjacent word lines can be biased using state-dependent pass voltages while other unselected word lines are biased using a standard or second set of pass voltages. Generally, each state-dependent pass voltage applied to a word line adjacent to the selected word line is larger than the second set of pass voltages applied to other unselected word lines, although this is not required. Other word lines, may also be biased using state-dependent pass voltages. System-level techniques are provided with or independently of state-dependent pass voltages to further reduce and manage read disturb. Techniques may account for data validity and memory write and erase cycles.

Abstract: A data storage device includes a non-volatile memory and a controller. A method includes receiving first data and second data from a host device. A first error-correcting code (ECC) codeword associated with the first data is written to a first word line of the non-volatile memory, and a second ECC codeword associated with the second data is written to a second word line of the non-volatile memory. The first ECC codeword includes a first bit and a second bit, and the second ECC codeword includes a third bit and a fourth bit. The method further includes writing parity information to a parity storage portion of the non-volatile memory that is distinct from the first word line and from the second word line. The parity information includes a parity bit that is based on the first bit, the second bit, the third bit, and the fourth bit.

Abstract: A NAND flash memory chip includes a first partition that has smaller memory cells, with smaller charge storage elements, and a second partition that has larger memory cells, with larger charge storage elements, in the same memory array. Data is selected for storage in the first or second partition according to characteristics, or expected characteristics, of the data.

Abstract: A memory system or flash memory device may include identify a bit error rate (BER) mapping for the memory. The BER mapping may be used for identifying erroneous bits, managing them, and using them for the system maintenance and system recovery. A complete BER map may be stored in main memory while a cached version of the BER map may be stored in random access memory (RAM). The cached version may identify only the top and bottom bits rather than the complete map. The cached BER map may be updated based on future reads and future programming may rely on the cached BER map for selecting blocks to program.