Abstract: The system obtains a first digital image and a hash associated with the first digital image, where the hash associated with the first digital image is a hash of analog values recorded by a sensor involved in generating the first digital image. Based on the hash, the system retrieves the analog values from a database. Based on the analog values, the system reconstructs a second digital image. The system determines whether the first digital image and the second digital image are substantially the same. Upon determining that the first digital image and the second digital image are substantially the same, the system provides a first notification that the first digital image is the same as the second digital image, otherwise the system provides a second notification that the first digital image is different from the second digital image.

Abstract: A semiconductor structure is provided that includes a device layer and a non-perpendicular (or non-orthogonal) wiring layer that includes a skip-level via that connects this wiring level to the device layer. The skip-level via passes through another wiring layer that is positioned between the non-perpendicular wiring layer and the device layer, without physically contacting any metal lines that are present in this another wiring layer.

Abstract: This disclosure is directed to methods and systems for validating digital images (e.g., originality of digital images, source of digital images) by validating non-fungible tokens. The methods and systems enable a device to obtain analog values using an imaging sensor, such as on a camera of the device. A first identification code and digital image can be generated using the analog values and can be used to mint a first non-fungible token (NFT). When a request is made to validate a second NFT containing the same digital image, e.g., claiming to be the original digital image, the analog values can be used to generate another hash, and compared against the identification (ID) value of the second NFT.

Abstract: Positional communication systems and methods include receiving a definition of a first geographic area including a first commercial location by a computer system and storing the first geographic area in a memory. The location of a mobile device in the possession of a customer is determined, and if the mobile device is determined to be at a location within the first geographic area, an incentive message for the customer to leave the location and go to a second commercial location is sent to the mobile device.

Abstract: An interconnect structure includes a first metallization layer, a second metallization layer, and a via metallization layer connecting the first metallization layer to the second metallization layer. The via metallization layer includes a metal via having a first portion extending in a first direction and a second portion extending from the first portion in a second direction different than the first direction.

Abstract: Methods, apparatuses, and systems for operating an electronic device as a web camera are disclosed. The disclosed embodiments relate to features that enable a user to operate a mobile device as a webcam. A smartphone case can hold a smartphone and be attached to a display, such as a laptop monitor or a flatscreen monitor, with a camera of the smartphone pointed at the user. The smartphone case can include a magnet, which triggers a Hall effect sensor inside the laptop or flatscreen monitor. The sensor can be used to trigger software that enables the smartphone and laptop or computer to pair with each other, e.g., by a Bluetooth handshake. The laptop or computer can accept a Wi-Fi or physical signal, such as via USB, from the smartphone and treat that input as a video stream into the laptop or computer.

Abstract: A vertical transport field effect transistor (VTFET) apparatus includes a fin-shaped channel structure; a gate stack that surrounds the channel structure; a top source/drain structure at a top end of the channel structure; a top interconnect layer above the top source/drain structure; a top contact that electrically connects the top source/drain structure to the top interconnect layer; a bottom source/drain structure at a bottom end of the channel structure; a backside interconnect layer below the bottom source/drain structure; and a backside contact that touches a bottom surface of the bottom source/drain structure and also touches a side surface of the bottom source/drain structure and electrically connects the bottom source/drain structure to the backside interconnect layer.

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a semiconductor wafer having a first transistor and a second transistor; a first source/drain (S/D) contact of the first transistor; a second S/D contact of the second transistor; and a cut region between the first S/D contact and the second S/D contact, wherein the cut region includes a liner of a first dielectric material and a filler of a second dielectric material that is different from the first dielectric material, the liner lining at least a part of the first S/D contact and a part of the second S/D contact, and the filler being directly adjacent to the liner and between the first S/D contact and the second S/D contact. A method of manufacturing the semiconductor structure is also provided.

Abstract: A perovskite material that has a perovskite crystal lattice having a formula of CxMyXz, and alkyl polyammonium cations disposed within or at a surface of the perovskite crystal lattice; wherein x, y, and z, are real numbers; C comprises one or more cations selected from the group consisting of Group 1 metals, Group 2 metals, ammonium, formamidinium, guanidinium, and ethene tetramine; M comprises one or more metals each selected from the group consisting of Be, Mg, Ca, Sr, Ba, Fe, Cd, Co, Ni, Cu, Ag, Au, Hg, Sn, Ge, Ga, Pb, In, Tl, Sb, Bi, Ti, Zn, Cd, Hg, and Zr, and combinations thereof; and X comprises one or more anions each selected from the group consisting of halides, pseudohalides, chalcogenides, and combinations thereof.

Abstract: An interconnect structure for an integrated circuit includes a plurality of first-type interconnect elements and a second-type of interconnect element which directly contact an underlying first-type interconnect element. The second-type interconnect element extends along a first axis to define a horizontal length and along a second axis to define a vertical height. The second-type interconnect element and the first-type interconnect element define a conductive via comprising a metal material extending continuously along the second axis from a base of the underlying first-type interconnect element and stopping at the upper surface of the second-type interconnect element. The vertical height of the second-type interconnect element is greater than the vertical height of the first-type interconnect elements.

Abstract: Semiconductor device and methods of forming the same include a semiconductor channel. A top source/drain structure is on the semiconductor channel. A bottom source/drain structure is under the semiconductor channel. The bottom source/drain structure includes a doped semiconductor part and a conductor part, with the conductor part covering a bottom surface of the doped semiconductor part.

Abstract: A VTFET is provided on a wafer. A backside power delivery network is on a backside of the wafer. A first backside contact is connected to a bottom source/drain region of the VTFET and a first portion of the backside power delivery network. A second backside contact is connected to top source/drain region of the VTFET and a second portion of the backside power delivery network.

Abstract: A semiconductor structure is presented including a device layer having a plurality of active devices, back-end-of-line (BEOL) components disposed under the device layer, a power distribution network (PDN) disposed over the device layer, and backside transistors disposed on a single crystal silicon (Si) layer disposed over the PDN. A through silicon via (TSV) extends from the backside transistors disposed on the single crystal Si layer through the BEOL. An upper TSV (uTSV) extends from the PDN through the backside transistors disposed on the single crystal Si layer to additional interconnects.

Abstract: A VTFET is on a wafer and a backside power delivery network is on a backside of the wafer. A first backside contact is connected to a gate of the VTFET and a first portion of the backside power delivery network. The VTFET has a first width and the first width is a contacted poly pitch (CPP). The first backside contact may be at least the first width from the VTFET. The first backside contact may be double the first width from the VTFET.

Abstract: An interconnect structure includes a first metal layer comprising at least one metal wire with a first segment and a local extension having a width in a first direction that is larger than a width of the first segment. A second metal layer is on top or below the first metal layer comprising at least one metal wire. A via is connected between the at least one metal wire of the first metal layer and the at least one metal wire of the second metal layer.

Abstract: A vertical-transport field-effect transistor (VTFET) is on a wafer. The VTFET has a first width. The first width is a contacted poly pitch (CPP). A bottom source/drain region of the VTFET extends at least the first width from the VTFET. A contact from a frontside of the VTFET is connected to the bottom source/drain region.

Abstract: A method for forming a semiconductor device includes forming a front side of the semiconductor device, the front side comprising a metal wire M2, and a plurality of power rails coupled to the M2. Further, the method includes forming a through silicon via (TSV) from a back side of the semiconductor device to the front side, the TSV connecting a first power rail of the front side with a metal wire M1 on the back side. Further, the method includes forming a power delivery network on the back side, the TSV providing power from the power delivery network to the front side.

Abstract: A visor is provided that is adapted to be mounted on a binocular indirect ophthalmoscope. The visor includes: a visor body shaped to conform with at least a portion of the binocular indirect ophthalmoscope; a visor attachment portion located between the visor body and one of a headband, instrument housing, or instrument housing strut of the binocular indirect ophthalmoscope when the visor is mounted on the binocular indirect ophthalmoscope. The visor is mountable on the binocular indirect ophthalmoscope such that the visor body is located in front of a substantial portion of a wearer of the binocular indirect ophthalmoscope. The visor is located on the binocular indirect ophthalmoscope such that the visor does not interfere with operation of the binocular indirect ophthalmoscope during operation of the binocular indirect ophthalmoscope.

Abstract: An interconnect structure for connecting an upper wiring line to a lower wiring line includes a via connecting a lower portion of the upper wiring line with an upper surface of the lower wiring line and a wrap-around via portion formed integrally with the via, the wrap-around portion extending along and electrically contacting a portion of the sides of the lower wiring line.

Abstract: A semiconductor device includes: a first via level forming a bottom jumper configured to provide an output; a first set of two or more first metallization tracks overlying the first via level; a second via level forming a first top jumper overlying the first set of two or more first metallization tracks; and a second metallization track overlying the second via level.