Patents by Inventor Nicolas Gani
Nicolas Gani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9633846Abstract: The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers. The plasma grid assembly may include one or more plasma grids having slots of a particular aspect ratio, which allow certain species to pass through from the upper sub-chamber to the lower sub-chamber. In some cases, an electron-ion plasma is generated in the upper sub-chamber. Electrons that make it through the grid to the lower sub-chamber are cooled as they pass through. In some cases, this results in an ion-ion plasma in the lower sub-chamber. The ion-ion plasma may be used to advantage in a variety of etching processes.Type: GrantFiled: November 30, 2015Date of Patent: April 25, 2017Assignee: Lam Research CorporationInventors: Alex Paterson, Do Young Kim, Gowri Kamarthy, Helene Del Puppo, Jen-Kan Yu, Monica Titus, Radhika Mani, Noel Yui Sun, Nicolas Gani, Yoshie Kimura, Ting-Ying Chung
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Publication number: 20170011891Abstract: A method and apparatus are provided for plasma etching a substrate in a processing chamber. A focus ring assembly circumscribes a substrate support, providing uniform processing conditions near the edge of the substrate. The focus ring assembly comprises two rings, a first ring and a second ring, the first ring comprising quartz, and the second ring comprising monocrystalline silicon, silicon carbide, silicon nitride, silicon oxycarbide, silicon oxynitride, or combinations thereof. The second ring is disposed above the first ring near the edge of the substrate, and creates a uniform electric field and gas composition above the edge of the substrate that results in uniform etching across the substrate surface.Type: ApplicationFiled: September 26, 2016Publication date: January 12, 2017Inventors: Edward P. HAMMOND, IV, Jing ZOU, Rodolfo P. BELEN, Meihua SHEN, Nicolas GANI, Andrew NGUYEN, David PALAGASHVILI, Michael D. WILLWERTH
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Patent number: 9533332Abstract: Embodiments of the invention include methods for in-situ chamber dry cleaning a plasma processing chamber utilized for gate structure fabrication process in semiconductor devices. In one embodiment, a method for in-situ chamber dry clean includes supplying a first cleaning gas including at least a boron containing gas into a processing chamber in absence of a substrate disposed therein, supplying a second cleaning gas including at least a halogen containing gas into the processing chamber in absence of the substrate, and supplying a third cleaning gas including at least an oxygen containing gas into the processing chamber in absence of the substrate.Type: GrantFiled: September 13, 2012Date of Patent: January 3, 2017Assignee: Applied Materials, Inc.Inventors: Noel Sun, Meihua Shen, Nicolas Gani, Chung Nang Liu, Radhika C. Mani
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Patent number: 9305797Abstract: Methods of polysilicon over-etch using hydrogen diluted plasma for three-dimensional gate etch are described. In an example, a method of forming a three-dimensional gate structure includes performing a main plasma etch on a masked polysilicon layer formed over a semiconductor fin. The method also includes, subsequently, performing a plasma over etch on the masked polysilicon layer based on a plasma generated from gaseous composition including hydrogen gas (H2).Type: GrantFiled: January 15, 2014Date of Patent: April 5, 2016Assignee: Applied Materials, Inc.Inventors: Radhika C. Mani, Nicolas Gani
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Publication number: 20160086795Abstract: The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers. The plasma grid assembly may include one or more plasma grids having slots of a particular aspect ratio, which allow certain species to pass through from the upper sub-chamber to the lower sub-chamber. In some cases, an electron-ion plasma is generated in the upper sub-chamber. Electrons that make it through the grid to the lower sub-chamber are cooled as they pass through. In some cases, this results in an ion-ion plasma in the lower sub-chamber. The ion-ion plasma may be used to advantage in a variety of etching processes.Type: ApplicationFiled: November 30, 2015Publication date: March 24, 2016Inventors: Alex Paterson, Do Young Kim, Gowri Kamarthy, Helene Del Puppo, Jen-Kan Yu, Monica Titus, Radhika Mani, Noel Yui Sun, Nicolas Gani, Yoshie Kimura, Ting-Ying Chung
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Patent number: 9230819Abstract: The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers. The plasma grid assembly may include one or more plasma grids having slots of a particular aspect ratio, which allow certain species to pass through from the upper sub-chamber to the lower sub-chamber. In some cases, an electron-ion plasma is generated in the upper sub-chamber. Electrons that make it through the grid to the lower sub-chamber are cooled as they pass through. In some cases, this results in an ion-ion plasma in the lower sub-chamber. The ion-ion plasma may be used to advantage in a variety of etching processes.Type: GrantFiled: February 19, 2014Date of Patent: January 5, 2016Assignee: Lam Research CorporationInventors: Alex Paterson, Do Young Kim, Gowri Kamarthy, Helene Del Puppo, Jen-Kan Yu, Monica Titus, Radhika Mani, Noel Yui Sun, Nicolas Gani, Yoshie Kimura, Ting-Ying Chung
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Publication number: 20140302678Abstract: The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers. The plasma grid assembly may include one or more plasma grids having slots of a particular aspect ratio, which allow certain species to pass through from the upper sub-chamber to the lower sub-chamber. In some cases, an electron-ion plasma is generated in the upper sub-chamber. Electrons that make it through the grid to the lower sub-chamber are cooled as they pass through. In some cases, this results in an ion-ion plasma in the lower sub-chamber. The ion-ion plasma may be used to advantage in a variety of etching processes.Type: ApplicationFiled: February 19, 2014Publication date: October 9, 2014Inventors: Alex Paterson, Do Young Kim, Gowri Kamarthy, Helene Del Puppo, Jen-Kan Yu, Monica Titus, Radhika Mani, Noel Yui Sun, Nicolas Gani, Yoshie Kimura, Ting-Ying Chung
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Publication number: 20140199849Abstract: Methods of polysilicon over-etch using hydrogen diluted plasma for three-dimensional gate etch are described. In an example, a method of forming a three-dimensional gate structure includes performing a main plasma etch on a masked polysilicon layer formed over a semiconductor fin. The method also includes, subsequently, performing a plasma over etch on the masked polysilicon layer based on a plasma generated from gaseous composition including hydrogen gas (H2).Type: ApplicationFiled: January 15, 2014Publication date: July 17, 2014Applicant: APPLIED MATERIALS, INC.Inventors: Radhika C. Mani, Nicolas Gani
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Patent number: 8722547Abstract: Wafers having a high K dielectric layer and an oxide or nitride containing layer are etched in an inductively coupled plasma processing chamber by applying a source power to generate an inductively coupled plasma, introducing into the chamber a gas including BCl3, setting the temperature of the wafer to be between 100° C. and 350° C., and etching the wafer with a selectivity of high K dielectric to oxide or nitride greater than 10:1. Wafers having an oxide layer and a nitride layer are etched in a reactive ion etch processing chamber by applying a bias power to the wafer, introducing into the chamber a gas including BCl3, setting the temperature of the wafer to be between 20° C. and 200° C., and etching the wafer with an oxide to nitride selectivity greater than 10:1.Type: GrantFiled: April 17, 2007Date of Patent: May 13, 2014Assignee: Applied Materials, Inc.Inventors: Radhika Mani, Nicolas Gani, Wei Liu, Meihua Shen, Shashank C. Deshmukh
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Publication number: 20130087174Abstract: Embodiments of the invention include methods for in-situ chamber dry cleaning a plasma processing chamber utilized for gate structure fabrication process in semiconductor devices. In one embodiment, a method for in-situ chamber dry clean includes supplying a first cleaning gas including at least a boron containing gas into a processing chamber in absence of a substrate disposed therein, supplying a second cleaning gas including at least a halogen containing gas into the processing chamber in absence of the substrate, and supplying a third cleaning gas including at least an oxygen containing gas into the processing chamber in absence of the substrate.Type: ApplicationFiled: September 13, 2012Publication date: April 11, 2013Applicant: Applied Materials, Inc.Inventors: Noel Sun, Meihua Shen, Nicolas Gani, Chung Nang Liu, Radhika C. Mani
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Publication number: 20120088371Abstract: Methods for etching substrates using a pulsed DC voltage are provided herein. In some embodiments, a method for method for etching a substrate disposed on a substrate support within a process chamber may include providing a process gas to the process chamber; forming a plasma from the process gas; applying a pulsed DC voltage to a first electrode disposed within the process chamber; and etching the substrate while applying the pulsed DC voltage.Type: ApplicationFiled: April 19, 2011Publication date: April 12, 2012Applicant: APPLIED MATERIALS, INC.Inventors: ALOK RANJAN, NICOLAS GANI, MEIHUA SHEN, ANISUL H. KHAN
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Patent number: 8133817Abstract: Methods for fabricating one or more shallow trench isolation (STI) structures are provided herein. In some embodiments, a method for fabricating one or more shallow trench isolation (STI) structures may include providing a substrate having a patterned mask layer disposed thereon to define one or more STI structures. The substrate may be etched using a plasma formed from a process gas mixture to form one or more STI structures on the substrate, wherein the process gas mixture comprises a fluorine-containing gas and either a fluorocarbon-containing gas or a hydrofluorocarbon-containing gas.Type: GrantFiled: November 30, 2008Date of Patent: March 13, 2012Assignee: Applied Materials, Inc.Inventors: Hiroki Sasano, Meihua Shen, Radhika Mani, Sunil Srinivasan, Daehee Weon, Nicolas Gani, Shashank Deshmukh, Anisul Khan
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Patent number: 8101525Abstract: Methods for fabricating a semiconductor device having a lanthanum-family-based oxide layer are described. A gate stack having a lanthanum-family-based oxide layer is provided above a substrate. At least a portion of the lanthanum-family-based oxide layer is modified to form a lanthanum-family-based halide portion. The lanthanum-family-based halide portion is removed with a water vapor treatment.Type: GrantFiled: February 13, 2009Date of Patent: January 24, 2012Assignee: Applied Materials, Inc.Inventors: Meihua Shen, Noel Sun, Nicolas Gani, Han-Hsiang Chen, Eric Pei, Weimin Zeng, Thorsten B. Lill, Uday Mitra, Ellie Y. Yieh
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Patent number: 7910488Abstract: Methods for etching, such as for fabricating a CMOS logic gate are provided herein. In some embodiments, a method of etching includes (a) providing a substrate having a first stack and a second stack disposed thereupon, the first stack comprising a high-k dielectric layer, a metal layer formed over the high-k dielectric layer, and a first polysilicon layer formed over the metal layer, the second stack comprising a second polysilicon layer, wherein the first and second stacks are substantially equal in thickness; (b) simultaneously etching a first feature in the first polysilicon layer and a second feature in the second polysilicon layer until the metal layer in the first stack is exposed; (c) simultaneously etching the metal layer and second polysilicon layer to extend the respective first and second features into the first and second stacks; and (d) etching the high-k dielectric layer.Type: GrantFiled: July 12, 2007Date of Patent: March 22, 2011Assignee: Applied Materials, Inc.Inventors: Nicolas Gani, Meihua Shen, Shashank Deshmukh
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Publication number: 20100210112Abstract: Methods for fabricating a semiconductor device having a lanthanum-family-based oxide layer are described. A gate stack having a lanthanum-family-based oxide layer is provided above a substrate. At least a portion of the lanthanum-family-based oxide layer is modified to form a lanthanum-family-based halide portion. The lanthanum-family-based halide portion is removed with a water vapor treatment.Type: ApplicationFiled: February 13, 2009Publication date: August 19, 2010Applicant: Applied Materials, Inc.Inventors: Meihua Shen, Noel Sun, Nicolas Gani, Han-Hsiang Chen, Eric Pei, Weimin Zeng, Thorsten B. Lill, Uday Mitra, Ellie Y. Yieh
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Patent number: 7648914Abstract: Embodiments of the invention generally provide methods for etching a substrate. In one embodiment, the method includes determining a substrate temperature target profile that corresponds to a uniform deposition rate of etch by-products on a substrate, preferentially regulating a temperature of a first portion of a substrate support relative to a second portion of the substrate support to obtain the substrate temperature target profile on the substrate, and etching the substrate on the preferentially regulated substrate support. In another embodiment, the method includes providing a substrate in a processing chamber having a selectable distribution of species within the processing chamber and a substrate support with lateral temperature control, wherein a temperature profile induced by the substrate support and a selection of species distribution comprise a control parameter set, etching a first layer of material and etching a second layer of material respectively using different control parameter sets.Type: GrantFiled: March 2, 2006Date of Patent: January 19, 2010Assignee: Applied Materials, Inc.Inventors: Thomas J. Kropewnicki, Theodoros Panagopoulos, Nicolas Gani, Wilfred Pau, Meihua Shen, John P. Holland
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Publication number: 20090221149Abstract: An apparatus having a multiple gas injection port system for providing a high uniform etching rate across the substrate is provided. In one embodiment, the apparatus includes a nozzle in the semiconductor processing apparatus having a hollow cylindrical body having a first outer diameter defining a hollow cylindrical sleeve and a second outer diameter defining a tip, a longitudinal passage formed longitudinally through the body of the hollow cylindrical sleeve and at least partially extending to the tip, and a lateral passage formed in the tip coupled to the longitudinal passage, the lateral passage extending outward from the longitudinal passage having an opening formed on an outer surface of the tip.Type: ApplicationFiled: February 28, 2008Publication date: September 3, 2009Inventors: Edward P. Hammond, IV, Rodolfo P. Belen, Nicolas Gani, Jing Zou, Meihua Shen, Michael D. Willwerth, David Palagashvili
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Publication number: 20090221150Abstract: A method and apparatus are provided for plasma etching a substrate in a processing chamber. A focus ring assembly circumscribes a substrate support, providing uniform processing conditions near the edge of the substrate. The focus ring assembly comprises two rings, a first ring and a second ring, the first ring comprising quartz, and the second ring comprising monocrystalline silicon, silicon carbide, silicon nitride, silicon oxycarbide, silicon oxynitride, or combinations thereof. The second ring is disposed above the first ring near the edge of the substrate, and creates a uniform electric field and gas composition above the edge of the substrate that results in uniform etching across the substrate surface.Type: ApplicationFiled: February 27, 2009Publication date: September 3, 2009Applicant: APPLIED MATERIALS, INC.Inventors: Edward P. Hammond, IV, Jing Zou, Rodolfo P. Belen, Meihua Shen, Nicolas Gani, Andrew Nguyen, David Palagashvili, Michael D. Willwerth
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Publication number: 20090170333Abstract: Methods for fabricating one or more shallow trench isolation (STI) structures are provided herein. In some embodiments, a method for fabricating one or more shallow trench isolation (STI) structures may include providing a substrate having a patterned mask layer disposed thereon to define one or more STI structures. The substrate may be etched using a plasma formed from a process gas mixture to form one or more STI structures on the substrate, wherein the process gas mixture comprises a fluorine-containing gas and either a fluorocarbon-containing gas or a hydrofluorocarbon-containing gas.Type: ApplicationFiled: November 30, 2008Publication date: July 2, 2009Inventors: Hiroki Sasano, Meihua Shen, Radhika Mani, Sunil Srinivasan, Daehee Weon, Nicolas Gani, Shashank Deshmukh, Anisul Khan
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Publication number: 20090017633Abstract: Methods for etching, such as for fabricating a CMOS logic gate are provided herein. In some embodiments, a method of etching includes (a) providing a substrate having a first stack and a second stack disposed thereupon, the first stack comprising a high-k dielectric layer, a metal layer formed over the high-k dielectric layer, and a first polysilicon layer formed over the metal layer, the second stack comprising a second polysilicon layer, wherein the first and second stacks are substantially equal in thickness; (b) simultaneously etching a first feature in the first polysilicon layer and a second feature in the second polysilicon layer until the metal layer in the first stack is exposed; (c) simultaneously etching the metal layer and second polysilicon layer to extend the respective first and second features into the first and second stacks; and (d) etching the high-k dielectric layer.Type: ApplicationFiled: July 12, 2007Publication date: January 15, 2009Applicant: APPLIED MATERIALS, INC.Inventors: NICOLAS GANI, Meihua Shen, Shashank Deshmukh