Patents by Inventor Nihad Hadzic
Nihad Hadzic has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11882645Abstract: A laminate carrier-like module lid including multiple laminate layers of non-conductive materials stacked one atop another, sensor circuitry embedded within the laminate carrier-like module lid, the sensor circuitry providing a continuous electrical circuit surrounding the electronic components of the multi-chip module package, and thermal circuitry embedded within the laminate carrier-like module lid, the thermal circuitry comprising solid copper traces to thermally conduct heat from the electronic components of the multi-chip module package.Type: GrantFiled: October 22, 2021Date of Patent: January 23, 2024Assignee: International Business Machines CorporationInventors: Sushumna Iruvanti, James Busby, Philipp K Buchling Rego, Steven Paul Ostrander, Thomas Anthony Wassick, William Santiago-Fernandez, Nihad Hadzic
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Publication number: 20230130104Abstract: A laminate carrier-like module lid including multiple laminate layers of non-conductive materials stacked one atop another, sensor circuitry embedded within the laminate carrier-like module lid, the sensor circuitry providing a continuous electrical circuit surrounding the electronic components of the multi-chip module package, and thermal circuitry embedded within the laminate carrier-like module lid, the thermal circuitry comprising solid copper traces to thermally conduct heat from the electronic components of the multi-chip module package.Type: ApplicationFiled: October 22, 2021Publication date: April 27, 2023Inventors: Sushumna Iruvanti, James Busby, Philipp K. Buchling Rego, Steven Paul Ostrander, Thomas Anthony Wassick, William Santiago-Fernandez, Nihad Hadzic
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Patent number: 11301215Abstract: A computer-implemented method for generating one or more random numbers includes configuring a mapper to feed inputs of a random number generation system using a subset of noise sources from multiple noise sources. The random number generation system generates a random number based on the inputs. The method further includes evaluating the subset of noise sources and detecting that a first noise source from the subset of noise sources has degraded in quality. The method further includes evaluating a second noise source from the available noise sources, the second noise source not being in the subset of noise sources. In response to the second noise source satisfying a predetermined threshold criterion, the first noise source is replaced with the second in the subset of noise sources for providing random bit streams to facilitate generating the random number by the random number generation system.Type: GrantFiled: January 27, 2020Date of Patent: April 12, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kirk David Lamb, Nihad Hadzic
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Publication number: 20210232367Abstract: A computer-implemented method for generating one or more random numbers includes configuring a mapper to feed inputs of a random number generation system using a subset of noise sources from multiple noise sources. The random number generation system generates a random number based on the inputs. The method further includes evaluating the subset of noise sources and detecting that a first noise source from the subset of noise sources has degraded in quality. The method further includes evaluating a second noise source from the available noise sources, the second noise source not being in the subset of noise sources. In response to the second noise source satisfying a predetermined threshold criterion, the first noise source is replaced with the second in the subset of noise sources for providing random bit streams to facilitate generating the random number by the random number generation system.Type: ApplicationFiled: January 27, 2020Publication date: July 29, 2021Inventors: KIRK DAVID LAMB, NIHAD HADZIC
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Patent number: 10915463Abstract: A method includes determining, by a tracker controller of a hardware security module, that a first processor has submitted a first request to access a computing resource. The method also includes determining, by the tracker controller, whether the first request and a second request both request access to the same computing resource. The second request is submitted by a second processor. The method also includes preventing access to the computing resource based on a determination that the first request and the second request do not request access to the same computing resource. The method also includes permitting access to the computing resource based on a determination that the first request and the second request both request access to the same computing resource.Type: GrantFiled: April 28, 2017Date of Patent: February 9, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Silvio Dragone, Nihad Hadzic, William Santiago Fernandez, Tamas Visegrady
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Patent number: 10809929Abstract: System, methods, and media are provided for enforcing segmentation of multi-tenant data. An example method includes informing hardware of direct memory access (DMA) segmented regions, in which the hardware is informed of software-specified size and count parameters relating to DMA windows. Identifying an originating DMA window for each DMA descriptor and referenced data. Verifying that contents of one or more DMA transfers are entirely from memory controlled by a single process. Setting DMA window-describing registers based the software-specified size and count parameters. Enforcing restrictions, based on the DMA window-describing registers, for DMA requests relating to the DMA windows as DMA requests are received.Type: GrantFiled: November 30, 2018Date of Patent: October 20, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: William Santiago Fernandez, Tamas Visegrady, Silvio Dragone, Nihad Hadzic
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Patent number: 10719454Abstract: A method includes determining, by a tracker controller of a hardware security module, that a first processor has submitted a first request to access a computing resource. The method also includes determining, by the tracker controller, whether the first request and a second request both request access to the same computing resource. The second request is submitted by a second processor. The method also includes preventing access to the computing resource based on a determination that the first request and the second request do not request access to the same computing resource. The method also includes permitting access to the computing resource based on a determination that the first request and the second request both request access to the same computing resource.Type: GrantFiled: November 6, 2017Date of Patent: July 21, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Silvio Dragone, Nihad Hadzic, William Santiago Fernandez, Tamas Visegrady
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Publication number: 20200174688Abstract: System, methods, and media are provided for enforcing segmentation of multi-tenant data. An example method includes informing hardware of direct memory access (DMA) segmented regions, in which the hardware is informed of software-specified size and count parameters relating to DMA windows. Identifying an originating DMA window for each DMA descriptor and referenced data. Verifying that contents of one or more DMA transfers are entirely from memory controlled by a single process. Setting DMA window-describing registers based the software-specified size and count parameters. Enforcing restrictions, based on the DMA window-describing registers, for DMA requests relating to the DMA windows as DMA requests are received.Type: ApplicationFiled: November 30, 2018Publication date: June 4, 2020Inventors: William Santiago Fernandez, Tamas Visegrady, Silvio Dragone, Nihad Hadzic
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Patent number: 10586056Abstract: A method includes determining, by a persistent memory lockstep unit of a hardware security module, that a first processor is attempting to change a state of the hardware security module. The method also includes determining, by the persistent memory lockstep unit, whether a second processor has attempted the same change. The method also includes preventing the change until both the first processor and the second processor have attempted the same change. The method also includes permitting the change to the state of the hardware security module based on a determination that both the first processor and the second processor have both attempted the same change.Type: GrantFiled: November 6, 2017Date of Patent: March 10, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Silvio Dragone, Nihad Hadzic, William Santiago Fernandez, Tamas Visegrady
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Patent number: 10360393Abstract: A method includes determining, by a persistent memory lockstep unit of a hardware security module, that a first processor is attempting to change a state of the hardware security module. The method also includes determining, by the persistent memory lockstep unit, whether a second processor has attempted the same change. The method also includes preventing the change until both the first processor and the second processor have attempted the same change. The method also includes permitting the change to the state of the hardware security module based on a determination that both the first processor and the second processor have both attempted the same change.Type: GrantFiled: April 28, 2017Date of Patent: July 23, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Silvio Dragone, Nihad Hadzic, William Santiago Fernandez, Tamas Visegrady
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Publication number: 20180314839Abstract: A method includes determining, by a persistent memory lockstep unit of a hardware security module, that a first processor is attempting to change a state of the hardware security module. The method also includes determining, by the persistent memory lockstep unit, whether a second processor has attempted the same change. The method also includes preventing the change until both the first processor and the second processor have attempted the same change. The method also includes permitting the change to the state of the hardware security module based on a determination that both the first processor and the second processor have both attempted the same change.Type: ApplicationFiled: April 28, 2017Publication date: November 1, 2018Inventors: Silvio Dragone, Nihad Hadzic, William Santiago Fernandez, Tamas Visegrady
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Publication number: 20180314840Abstract: A method includes determining, by a persistent memory lockstep unit of a hardware security module, that a first processor is attempting to change a state of the hardware security module. The method also includes determining, by the persistent memory lockstep unit, whether a second processor has attempted the same change. The method also includes preventing the change until both the first processor and the second processor have attempted the same change. The method also includes permitting the change to the state of the hardware security module based on a determination that both the first processor and the second processor have both attempted the same change.Type: ApplicationFiled: November 6, 2017Publication date: November 1, 2018Inventors: Silvio Dragone, Nihad Hadzic, William Santiago Fernandez, Tamas Visegrady
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Publication number: 20180314649Abstract: A method includes determining, by a tracker controller of a hardware security module, that a first processor has submitted a first request to access a computing resource. The method also includes determining, by the tracker controller, whether the first request and a second request both request access to the same computing resource. The second request is submitted by a second processor. The method also includes preventing access to the computing resource based on a determination that the first request and the second request do not request access to the same computing resource. The method also includes permitting access to the computing resource based on a determination that the first request and the second request both request access to the same computing resource.Type: ApplicationFiled: April 28, 2017Publication date: November 1, 2018Inventors: Silvio Dragone, Nihad Hadzic, William Santiago Fernandez, Tamas Visegrady
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Publication number: 20180314650Abstract: A method includes determining, by a tracker controller of a hardware security module, that a first processor has submitted a first request to access a computing resource. The method also includes determining, by the tracker controller, whether the first request and a second request both request access to the same computing resource. The second request is submitted by a second processor. The method also includes preventing access to the computing resource based on a determination that the first request and the second request do not request access to the same computing resource. The method also includes permitting access to the computing resource based on a determination that the first request and the second request both request access to the same computing resource.Type: ApplicationFiled: November 6, 2017Publication date: November 1, 2018Inventors: Silvio Dragone, Nihad Hadzic, William Santiago Fernandez, Tamas Visegrady
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Patent number: 10108569Abstract: In one embodiment, a computer-implemented method includes assigning a time budget to each of a plurality of virtual functions in a single-root input/output (SRIOV) environment, where a first time budget of a first virtual function indicates a quantity of cycles on an engine of the SRIOV environment allowed to the first virtual function within a time slice. A plurality of requests issued by the plurality of virtual functions are selected by a computer processor, where the selecting excludes requests issued by virtual functions that have used their associated time budgets of cycles in a current time slice. The selected plurality of requests are delivered to the engine for processing. The time budgets of the virtual functions are reset and a new time slice begins, at the end of the current time slice.Type: GrantFiled: September 3, 2015Date of Patent: October 23, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mark A. Check, Vincenzo Condorelli, Nihad Hadzic, William Santiago Fernandez
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Patent number: 10102165Abstract: In one embodiment, a computer-implemented method includes assigning a time budget to each of a plurality of virtual functions in a single-root input/output (SRIOV) environment, where a first time budget of a first virtual function indicates a quantity of cycles on an engine of the SRIOV environment allowed to the first virtual function within a time slice. A plurality of requests issued by the plurality of virtual functions are selected by a computer processor, where the selecting excludes requests issued by virtual functions that have used their associated time budgets of cycles in a current time slice. The selected plurality of requests are delivered to the engine for processing. The time budgets of the virtual functions are reset and a new time slice begins, at the end of the current time slice.Type: GrantFiled: November 25, 2014Date of Patent: October 16, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mark A. Check, Vincenzo Condorelli, Nihad Hadzic, William Santiago Fernandez
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Patent number: 9535656Abstract: Embodiments relate to modular reductions. An aspect includes a system to perform modular reductions. The system includes a shift register to store an input string or number. The system also includes a plurality of processing elements arranged in a pipeline configuration to convert the input string to a predefined alphabet or to convert the number to a different base based on a plurality of modular reductions, an output of one of the plurality of processing elements being an input to a subsequent one of the plurality of processing elements in the pipeline as part of a recursive division, and an input of a first one of the plurality of processing elements in the pipeline being an output of the shift register.Type: GrantFiled: March 14, 2014Date of Patent: January 3, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Vincenzo Condorelli, Silvio Dragone, William Santiago Fernandez, Nihad Hadzic, Andrew R. Ranck
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Patent number: 9471276Abstract: Embodiments relate to modular reductions. An aspect includes a system to perform modular reductions. The system includes a shift register to store an input string or number. The system also includes a plurality of processing elements arranged in a pipeline configuration to convert the input string to a predefined alphabet or to convert the number to a different base based on a plurality of modular reductions, an output of one of the plurality of processing elements being an input to a subsequent one of the plurality of processing elements in the pipeline as part of a recursive division, and an input of a first one of the plurality of processing elements in the pipeline being an output of the shift register.Type: GrantFiled: April 5, 2016Date of Patent: October 18, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Vincenzo Condorelli, Silvio Dragone, William Santiago Fernandez, Nihad Hadzic, Andrew R. Ranck
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Publication number: 20160210119Abstract: Embodiments relate to modular reductions. An aspect includes a system to perform modular reductions. The system includes a shift register to store an input string or number. The system also includes a plurality of processing elements arranged in a pipeline configuration to convert the input string to a predefined alphabet or to convert the number to a different base based on a plurality of modular reductions, an output of one of the plurality of processing elements being an input to a subsequent one of the plurality of processing elements in the pipeline as part of a recursive division, and an input of a first one of the plurality of processing elements in the pipeline being an output of the shift register.Type: ApplicationFiled: April 5, 2016Publication date: July 21, 2016Inventors: Vincenzo Condorelli, Silvio Dragone, William Santiago Fernandez, Nihad Hadzic, Andrew R. Ranck
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Publication number: 20160147687Abstract: In one embodiment, a computer-implemented method includes assigning a time budget to each of a plurality of virtual functions in a single-root input/output (SRIOV) environment, where a first time budget of a first virtual function indicates a quantity of cycles on an engine of the SRIOV environment allowed to the first virtual function within a time slice. A plurality of requests issued by the plurality of virtual functions are selected by a computer processor, where the selecting excludes requests issued by virtual functions that have used their associated time budgets of cycles in a current time slice. The selected plurality of requests are delivered to the engine for processing. The time budgets of the virtual functions are reset and a new time slice begins, at the end of the current time slice.Type: ApplicationFiled: November 25, 2014Publication date: May 26, 2016Inventors: Mark A. Check, Vincenzo Condorelli, Nihad Hadzic, William Santiago Fernandez