Abstract: In one embodiment, a computer-implemented method includes assigning a time budget to each of a plurality of virtual functions in a single-root input/output (SRIOV) environment, where a first time budget of a first virtual function indicates a quantity of cycles on an engine of the SRIOV environment allowed to the first virtual function within a time slice. A plurality of requests issued by the plurality of virtual functions are selected by a computer processor, where the selecting excludes requests issued by virtual functions that have used their associated time budgets of cycles in a current time slice. The selected plurality of requests are delivered to the engine for processing. The time budgets of the virtual functions are reset and a new time slice begins, at the end of the current time slice.

Abstract: A calculation, prediction and validation method can include receiving a portion of a data packet in a data buffer, computing, in a processor, information related to the checksum of the data packet based on the portion of the data packet and processing the data packet in the processor.

Abstract: Embodiments relate to modular reductions. An aspect includes a system to perform modular reductions. The system includes a shift register to store an input string or number. The system also includes a plurality of processing elements arranged in a pipeline configuration to convert the input string to a predefined alphabet or to convert the number to a different base based on a plurality of modular reductions, an output of one of the plurality of processing elements being an input to a subsequent one of the plurality of processing elements in the pipeline as part of a recursive division, and an input of a first one of the plurality of processing elements in the pipeline being an output of the shift register.

Abstract: A computer-implemented method that includes creating a master copy of a header for all packets of a data transmission event, the master copy including a plurality of intact constant header information, the plurality of intact constant header information being constant for all packets of the data transmission event, storing unique header information for all packets of the data transmission event, the unique header information including information unique to at least one packet of the data transmission event, tokenizing identities of each packet of the data transmission event to create a tokenized packet ID for each packet, and indexing the stored unique header information based on the tokenizing. According to the method, at packet read-time, unique header information associated with the packet is overlayed onto the master copy to create a unique packet.

Abstract: Programmable hardware devices are re-programmed without system downtime. To re-program the device, the device is quiesced, state associated with the device is saved, updates are loaded, the state is restored and operations are resumed, all transparent to the system, except for a possible delay in the system.

Abstract: The method includes creating a master copy of a header for all packets of a data transmission event, the master copy including a plurality of intact constant header information, the plurality of intact constant header information being constant for all packets of the data transmission event, storing unique header information for all packets of the data transmission event, the unique header information including information unique to at least one packet of the data transmission event, tokenizing identities of each packet of the data transmission event to create a tokenized packet ID for each packet, and indexing the stored unique header information based on the tokenizing. A computer program product for directing a computer processor to perform a method. According to the method, at packet read-time, unique header information associated with the packet is overlayed onto the master copy to create a unique packet.

Abstract: Programmable hardware devices are re-programmed without system downtime. To re-program the device, the device is quiesced, state associated with the device is saved, updates are loaded, the state is restored and operations are resumed, all transparent to the system, except for a possible delay in the system.

Abstract: A calculation, prediction and validation method can include receiving a portion of a data packet in a data buffer, computing, in a processor, information related to the checksum of the data packet based on the portion of the data packet and processing the data packet in the processor.

Abstract: A checksum calculation, prediction and validation system includes a host system, a network interface, a reception pipeline disposed between the host system and network interface and configured to calculate an expected full checksum related to packets received in the host system and a transmission pipeline disposed between the host system and network interface and configured calculate factors related to packets for transmission on the network interface.

Abstract: A calculation, prediction and validation method can include receiving a portion of a data packet in a data buffer, computing, in a processor, information related to the checksum of the data packet based on the portion of the data packet and processing the data packet in the processor.

Abstract: Programmable hardware devices are re-programmed without system downtime. To re-program the device, the device is quiesced, state associated with the device is saved, updates are loaded, the state is restored and operations are resumed, all transparent to the system, except for a possible delay in the system.

Abstract: Programmable hardware devices are re-programmed without system downtime. To re-program the device, the device is quiesced, state associated with the device is saved, updates are loaded, the state is restored and operations are resumed, all transparent to the system, except for a possible delay in the system.

Abstract: A checksum calculation, prediction and validation system includes a host system, a network interface, a reception pipeline disposed between the host system and network interface and configured to calculate an expected full checksum related to packets received in the host system and a transmission pipeline disposed between the host system and network interface and configured calculate factors related to packets for transmission on the network interface.

Abstract: The method includes creating a master copy of a header for all packets of a data transmission event, the master copy including a plurality of intact constant header information, the plurality of intact constant header information being constant for all packets of the data transmission event, storing unique header information for all packets of the data transmission event, the unique header information including information unique to at least one packet of the data transmission event, tokenizing identities of each packet of the data transmission event to create a tokenized packet ID for each packet, and indexing the stored unique header information based on the tokenizing. A computer program product for directing a computer processor to perform a method. According to the method, at packet read-time, unique header information associated with the packet is overlayed onto the master copy to create a unique packet.

Abstract: A method and apparatus is disclosed for preventing the unintended retention of secret data caused by preferred state/burn-in in secure electronic modules. Sequentially storing the data and its inverse on alternating clock cycles, and by actively overwriting it to destroy it, prevents SRAM devices from developing a preferred state. By encrypting a relatively large amount of secret data with a master encryption key, and storing said master key in this non-preferred state storage, the electronic module conveniently extends this protection scheme to a large amount of data, without the overhead of investing or actively erasing the larger storage area.

Abstract: A tamper-proof cap adapted to be mounted on a large assembly for shielding a selected area of the large assembly is disclosed. The tamper-proof cap comprises a laminate stack-up structure wherein at least one open chamber is formed. The stack-up structure comprises at least two layers wherein tamper-proof layers are formed on top of the open chamber. A plurality of vias are disposed around the open chamber, forming with said tamper proof layers a tamper-proof structure around said open chamber. The vias are adapted for connecting the tamper-proof layers to the large assembly when the tamper-proof cap is mounted. In a preferred embodiment, the tamper-proof cap further comprises a shielding layer on top of the tamper-proof layer that are preferably done using conductive ink.

Abstract: A physically secure processing assembly is provided that includes dies mounted on a substrate so as to sandwich the electrical contacts of the dies between the dies and the substrate. The substrate is provided with substrate contacts and conductive pathways that are electrically coupled to the die contacts and extend through the substrate. Electrical conductors surround the conductive pathways. A monitoring circuit detects a break in continuity of one or more of the electrical conductors, and preferably renders the assembly inoperable. Preferably, an epoxy encapsulation is provided to prevent probing tools from being able to reach the die or substrate contacts.

Abstract: A method for embedding tamper proof layers and discrete components into a printed circuit board stack-up is disclosed. According to this method, a plating mask is applied on a base substrate to cover partially one of its faces. Conductive ink is then spread on this face so as to fill the gap formed by the plating mask. To obtain a uniform distribution of the conductive ink and then gel it, the conductive ink is preferably heated. A dielectric layer is applied on the conductive ink layer and the polymerization process is ended to obtain a strong adhesion between these two layers. In a preferred embodiment, conductive tracks are simultaneously designed on the other face of the base substrate to reduce thermo-mechanical strains and deformations.

Abstract: An operational status display for a nerve stimulator is located remote from the nerve stimulator. In one embodiment the display comprises a stand-alone discrete component that can be placed as desired by the nerve stimulator needle. In another embodiment, the display comprises an integral part of the nerve stimulator needle. The display can be alphanumeric or can comprise one or more discrete signal lights or other visual indicia. Color can be used to provide information regarding levels (intensity) of current, or the energy being provided to the needle and/or being delivered to the patient. In some embodiments these displays also provide information regarding the presence or absence of current and/or the polarity of the electricity then being provided to the nerve stimulator needle.

Abstract: A physically secure processing assembly is provided that includes dies mounted on a substrate so as to sandwich the electrical contacts of the dies between the dies and the substrate. The substrate is provided with substrate contacts and conductive pathways that are electrically coupled to the die contacts and extend through the substrate. Electrical conductors surround the conductive pathways. A monitoring circuit detects a break in continuity of one or more of the electrical conductors, and preferably renders the assembly inoperable. Preferably, an epoxy encapsulation is provided to prevent probing tools from being able to reach the die or substrate contacts.