Abstract: Techniques herein provide methods for depositing spin-on metal materials for creating metal hard mask (MHM) structures without voids in the deposition. This includes effective spin-on deposition of TiOx, ZrOx, SnOx, HFOx, TaOx, et cetera. Such materials can help to provide differentiation of material etch resistivity for differentiation. By enabling spin-on metal hard mask (MHM) for use with a multi-line layer, a slit-based or self-aligned blocking strategy can be effectively used. Techniques herein include identifying a fill material to fill particular openings in a given relief pattern, modifying a surface energy value of surfaces within the opening such that a contact angle value of an interface between the fill material in liquid form and the sidewall or floor surfaces enables gap-free or void-free filling.

Abstract: Techniques disclosed herein provide a method for substrate patterning that results in lines of non-uniform pitch (mixed pitch). Techniques can also enable advanced patterning options by selectively replacing lines of material in a multi-line layer. A multi-line layer is formed that has alternating lines of three different materials. One or more etch masks are used to selectively remove at least one uncovered line without removing other uncovered lines. Removed material is replaced with a fill material. Selective removal is executed using an etch mask as well as differing etch resistivities of the different lines of materials.

Abstract: An additional non-photoresist layer may be formed on patterned photoresist layers. The additional layer may be preferentially formed on the tops of the photoresist layer versus the sidewalls of the photoresist layer. In addition, the additional layer may be preferential formed on the tops of the photoresist layer versus exposed surfaces of layers underlying the photoresist layer. In this manner, the patterned structures formed by the photoresist layer are less likely to have line opens due to photoresist height variability or the relative thinness of the photoresist height used. Further, the formation of the additional layer may be through a cyclic deposition/trim process. The trim step of the cyclic process may also serve as a descum step that helps reduce line bridging and scumming. In one embodiment, the additional non-photoresist layer may be an organic polymer layer.

Abstract: Techniques herein include methods of processing photoresist patterns and photoresist materials for successful use in multi-patterning operations. Techniques include combinations of targeted deposition, curing, and trimming to provide a post-processed resist that effectively enables multi-patterning using photoresist materials to function as mandrels. Photoresist patterns and mandrels are hardened, strengthened, and/or dimensionally adjusted to provide desired dimensions and/or mandrels enabling straight sidewall spacers. Polymer is deposited with tapered profile to compensate for compressive stresses of various conformal or subsequent films to result in a vertical profile despite any compression.

Abstract: A semiconductor device including a substrate and a gate region of a field effect transistor formed on the substrate. The gate region includes vertically stacked nanowires having longitudinal axes that extend parallel with a working surface of the substrate. A given stack of vertically stacked nanowires includes at least two nanowires vertically aligned in which a p-type nanowire and an n-type nanowire are spatially separated from each other vertically. The semiconductor device further includes a step-shaped connecting structure formed within the gate region that electrically connects each nanowire to positions above the gate region. A first gate electrode has a step-shaped profile and connects to a first-level nanowire.

Abstract: Techniques herein provide an etch-based planarization technique. An initial film is deposited on a substrate. Deposition of this initial film results in a non-planar film because of differences in area density of underlying structures (for example, open areas compared to closely spaced trenches). Etch processes are executed that use a reverse lag RIE process to planarize the initial film, and then another coat of the film material can be deposited, resulting in a planar surface. Such techniques can planarized substrates without using chemical mechanical polishing (CMP).

Abstract: Techniques disclosed herein provide a method for substrate patterning that results in lines of non-uniform pitch (mixed pitch). Techniques can also enable advanced patterning options by selectively replacing lines of material in a multi-line layer. A multi-line layer is formed that has alternating lines of three different materials. One or more etch masks are used to selectively remove at least one uncovered line without removing other uncovered lines. Removed material is replaced with a fill material. Selective removal is executed using an etch mask as well as differing etch resistivities of the different lines of materials.

Abstract: Techniques herein include patterning processes to prevent over-etching for various multi-patterning processes. Multi-patterning processes typically involve creation of sidewall spacers and removal of mandrels on which sidewall spacers are formed. In some patterning flows gouging of underlying layers can occurs during the various multi-patterning steps. Techniques herein include methods to prevent such gouging by using a planarization layer recessed sufficiently to removed desired materials and protect others. Such techniques can remove bi-layer mandrels without gouging underlying layers.

Abstract: A formed back-end-of-line (BEOL) metal line layer may include a plurality of metal lines with dielectric oxide caps that are disposed in between each metal lines. To overlay an interconnecting layer of metal lines on a selected metal line of the BEOL metal line layer, a block copolymer (BCP) may be formed on a patterning layer. Thereafter, a selective etching of the formed BCP creates a recess above the selected metal line. The created recess facilitates the overlaying of the interconnecting layer of metal lines.

Abstract: Techniques herein use a self-alignment based process that enables single fin cutting (cutting a single fin among other fins) with overlay requirements relaxed by as much as three times. Embodiments can achieve this benefit by forming fins that use multiple different materials. For example, an array of fins can include parallel fins that alternate in type of material that comprises each fin. Different materials are selected that have different etch resistivities. With such a configuration, an etch mask that uncovers more than one fin (due to overlay error and/or lithographic resolution constraints) can nevertheless cut a desired fin using a combination of an etch mask and differing material resistivities.

Abstract: Techniques herein include a method of patterning a substrate that uses a self-alignment based process to align a via to odd and even trenches by using multiple different materials. Methods herein decompose or separate a via pattern into spacer side via and mandrel side via, and then sequentially access the spacer side and mandrel side respectively. With such a technique, overlay of via to grid is significantly improved. By using an additional memorization layer underneath a trench memorization layer and independently accessing the spacer side and mandrel side in the midst of a trench pattern, significant improvement in via alignment is achieved.

Abstract: A multiple patterning process is provided with a self-aligned blocking (SAB) technique. The SAB technique trades off difficult overlay requirements for more manageable etch selectivity requirements between the various layers utilized for the patterning process. As disclosed herein, damage to sidewalls resulting from etching at the self-aligned block masking step may still occur. Damage is repaired by providing a plug layer that fills the areas of the damaged spacers. The plug layer may be the same material as forms the spacers. In this manner, the fill process provides a self-healing mechanism for damaged spacers.

Abstract: Techniques herein provide an etch-based planarization technique. An initial film is deposited on a substrate. Deposition of this initial film results in a non-planar film because of differences in area density of underlying structures (for example, open areas compared to closely spaced trenches). Etch processes are executed that use a reverse lag RIE process to planarize the initial film, and then another coat of the film material can be deposited, resulting in a planar surface. Such techniques can planarized substrates without using chemical mechanical polishing (CMP).

Abstract: A method of forming a semiconductor device having a channel and a source-drain coupled to the channel. The method includes etching a channel region such that an end of the channel region forms a recess within a gate structure surrounding the channel region. An extension region is formed in contact with the channel region and at least partially filling the recess. Extension material of the extension region has a different composition from channel material of the channel region such that a strain is caused in the channel region. A source-drain region is in contact with the extension region and adjacent to the gate structure.

Abstract: A semiconductor device including a substrate and a gate region of a field effect transistor formed on the substrate. The gate region includes vertically stacked nanowires having longitudinal axes that extend parallel with a working surface of the substrate. A given stack of vertically stacked nanowires includes at least two nanowires vertically aligned in which a p-type nanowire and an n-type nanowire are spatially separated from each other vertically. The semiconductor device further Includes a step-shaped connecting structure formed within the gate region that electrically connects each nanowire to positions above the gate region. A first gate electrode has a step-shaped profile and connects to a first-level nanowire.

Abstract: Provide is a method of patterning spacers, the method comprising: providing an initial patterned structure in a substrate in a processing chamber, the initial patterned structure comprising an organic mandrel and an underlying layer; exposing the patterned structure in a direct current superposition (DCS) plasma treatment process, the process depositing a layer of a first material on the initial patterned structure; performing an atomic layer conformal deposition process using a second material, the first material providing protection to the organic mandrel at the beginning of the atomic layer conformal deposition process; performing a post spacer etch mandrel pull process, the process creating a final patterned structure with a target final sidewall angle; concurrently controlling integration operating variables in the exposing the patterned structure, the atomic layer conformal deposition process, and the post spacer etch mandrel pull process in order to meet the target final sidewall angle and other integr

Abstract: Techniques herein enable integrating stack materials and multiple color materials that require no corrosive gases for etching. Techniques enable a multi-line layer for self-aligned pattern shrinking in which all layers or colors or materials can be limited to silicon-containing materials and organic materials. Such techniques enable self-aligned block integration for 5 nm back-end-of-line trench patterning with an all non-corrosive etch compatible stack for self-aligned block. Embodiments include using lines of a same material but at different heights to provided etch selectivity to one of several lines based on type of material and/or height of material and etch rate.

Abstract: Techniques herein provide a process to reform or flatten asymmetric spacers to form a square profile which creates symmetric spacers for accurate pattern transfer. Initial spacer formation typically results in spacer profiles with a curved or sloped top surfaces. This asymmetric top surface is isolated while protecting a remaining lower portion of the spacer. The top surface is removed using a plasma processing step resulting in spacers having a squared profile that enables further patterning and/or accurate pattern transfer.

Abstract: Embodiments of the invention provide a substrate processing method for bottom-up formation of a film in a recessed feature. According to one embodiment, the method includes providing a substrate containing a first layer and a second layer on the first layer, the second layer having a recessed feature extending through the second layer, and depositing a non-conformal mask layer on the substrate, where the mask layer has an overhang at an opening of the recessed feature. The method further includes removing the mask layer from a bottom of the recessed feature, while maintaining at least a portion of the overhang at the opening, selectively depositing a film on the bottom of the recessed feature, and removing the mask layer overhang from the substrate. The processing steps may be repeated at least once until the film has a desired thickness in the recessed feature.

Abstract: Provided is a method for increasing pattern density of a structure using an integration scheme and perform pitch splitting at the resist level without the use of hard mandrels, the method comprising: providing a substrate having a patterned resist layer and an underlying layer comprising a silicon anti-reflective coating layer, an amorphous layer, and a target layer; performing a resist hardening process; performing a first conformal spacer deposition using an atomic layer deposition technique with an oxide, performing a spacer first reactive ion etch process and a first pull process on the first conformal layer, performing a second conformal spacer deposition using titanium oxide; performing a second spacer RIE process and a second pull process, generating a second spacer pattern; and transferring the second spacer pattern into the target layer, wherein targets include patterning uniformity, pulldown of structures, slimming of structures, aspect ratio of structures, and line width roughness.